1 // SPDX-License-Identifier: GPL-2.0+
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Common Clock Framework [CCF] driver for Sandbox
14 #include <clk-uclass.h>
15 #include <dm/devres.h>
16 #include <linux/clk-provider.h>
17 #include <sandbox-clk.h>
18 #include <linux/err.h>
21 * Sandbox implementation of CCF primitives necessary for clk-uclass testing
23 * --- Sandbox PLLv3 ---
31 int sandbox_clk_enable_count(struct clk *clk)
33 struct clk *clkp = NULL;
36 ret = clk_get_by_id(clk->id, &clkp);
40 return clkp->enable_count;
43 static ulong clk_pllv3_get_rate(struct clk *clk)
45 unsigned long parent_rate = clk_get_parent_rate(clk);
47 return parent_rate * 24;
50 static const struct clk_ops clk_pllv3_generic_ops = {
51 .get_rate = clk_pllv3_get_rate,
54 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
55 const char *parent_name, void __iomem *base,
58 struct clk_pllv3 *pll;
60 char *drv_name = "sandbox_clk_pllv3";
63 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
65 return ERR_PTR(-ENOMEM);
67 pll->div_mask = div_mask;
70 ret = clk_register(clk, drv_name, name, parent_name);
79 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
80 .name = "sandbox_clk_pllv3",
82 .ops = &clk_pllv3_generic_ops,
85 /* --- Sandbox PLLv3 --- */
86 /* --- Sandbox Gate --- */
92 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
94 static int clk_gate2_enable(struct clk *clk)
96 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
102 static int clk_gate2_disable(struct clk *clk)
104 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
110 static const struct clk_ops clk_gate2_ops = {
111 .enable = clk_gate2_enable,
112 .disable = clk_gate2_disable,
113 .get_rate = clk_generic_get_rate,
116 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
117 const char *parent_name,
118 unsigned long flags, void __iomem *reg,
119 u8 bit_idx, u8 cgr_val,
122 struct clk_gate2 *gate;
126 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
128 return ERR_PTR(-ENOMEM);
133 ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
142 U_BOOT_DRIVER(sandbox_clk_gate2) = {
143 .name = "sandbox_clk_gate2",
145 .ops = &clk_gate2_ops,
148 static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
150 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
151 struct clk_composite *composite = (struct clk_composite *)clk->data;
152 ulong parent_rate = clk_get_parent_rate(&composite->clk);
155 val = divider->io_divider_val;
156 val >>= divider->shift;
157 val &= clk_div_mask(divider->width);
159 return divider_recalc_rate(clk, parent_rate, val, divider->table,
160 divider->flags, divider->width);
163 static const struct clk_ops sandbox_clk_composite_divider_ops = {
164 .get_rate = sandbox_clk_composite_divider_recalc_rate,
167 struct clk *sandbox_clk_composite(const char *name,
168 const char * const *parent_names,
169 int num_parents, void __iomem *reg,
172 struct clk *clk = ERR_PTR(-ENOMEM);
173 struct clk_divider *div = NULL;
174 struct clk_gate *gate = NULL;
175 struct clk_mux *mux = NULL;
177 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
184 mux->num_parents = num_parents;
186 mux->parent_names = parent_names;
188 div = kzalloc(sizeof(*div), GFP_KERNEL);
195 div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
197 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
205 clk = clk_register_composite(NULL, name,
206 parent_names, num_parents,
207 &mux->clk, &clk_mux_ops, &div->clk,
208 &sandbox_clk_composite_divider_ops,
209 &gate->clk, &clk_gate_ops, flags);
219 return ERR_CAST(clk);
222 /* --- Sandbox Gate --- */
223 /* The CCF core driver itself */
224 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
225 { .compatible = "sandbox,clk-ccf" },
229 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
230 static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
232 static int sandbox_clk_ccf_probe(struct udevice *dev)
237 clk_dm(SANDBOX_CLK_PLL3,
238 sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
241 clk_dm(SANDBOX_CLK_PLL3_60M,
242 sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
244 clk_dm(SANDBOX_CLK_PLL3_80M,
245 sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
247 /* The HW adds +1 to the divider value (2+1) is the divider */
249 clk_dm(SANDBOX_CLK_ECSPI_ROOT,
250 sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6));
252 clk_dm(SANDBOX_CLK_ECSPI1,
253 sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
255 /* Select 'pll3_60m' */
257 clk_dm(SANDBOX_CLK_USDHC1_SEL,
258 sandbox_clk_mux("usdhc1_sel", ®, 16, 1, usdhc_sels,
259 ARRAY_SIZE(usdhc_sels)));
261 /* Select 'pll3_80m' */
263 clk_dm(SANDBOX_CLK_USDHC2_SEL,
264 sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
265 ARRAY_SIZE(usdhc_sels)));
267 reg = BIT(28) | BIT(24) | BIT(16);
268 clk_dm(SANDBOX_CLK_I2C,
269 sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
272 clk_dm(SANDBOX_CLK_I2C_ROOT,
273 sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
278 U_BOOT_DRIVER(sandbox_clk_ccf) = {
279 .name = "sandbox_clk_ccf",
281 .probe = sandbox_clk_ccf_probe,
282 .of_match = sandbox_clk_ccf_test_ids,