drivers/clk/clk_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/cru_rk3288.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dm/device-internal.h>
  19 #include <dm/lists.h>
  20 #include <dm/uclass-internal.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct rk3288_clk_plat {
  25         enum rk_clk_id clk_id;
  26 };
  27
  28 struct rk3288_clk_priv {
  29         struct rk3288_grf *grf;
  30         struct rk3288_cru *cru;
  31         ulong rate;
  32 };
  33
  34 struct pll_div {
  35         u32 nr;
  36         u32 nf;
  37         u32 no;
  38 };
  39
  40 enum {
  41         VCO_MAX_HZ      = 2200U * 1000000,
  42         VCO_MIN_HZ      = 440 * 1000000,
  43         OUTPUT_MAX_HZ   = 2200U * 1000000,
  44         OUTPUT_MIN_HZ   = 27500000,
  45         FREF_MAX_HZ     = 2200U * 1000000,
  46         FREF_MIN_HZ     = 269 * 1000000,
  47 };
  48
  49 enum {
  50         /* PLL CON0 */
  51         PLL_OD_MASK             = 0x0f,
  52
  53         /* PLL CON1 */
  54         PLL_NF_MASK             = 0x1fff,
  55
  56         /* PLL CON2 */
  57         PLL_BWADJ_MASK          = 0x0fff,
  58
  59         /* PLL CON3 */
  60         PLL_RESET_SHIFT         = 5,
  61
  62         /* CLKSEL0 */
  63         CORE_SEL_PLL_MASK       = 1,
  64         CORE_SEL_PLL_SHIFT      = 15,
  65         A17_DIV_MASK            = 0x1f,
  66         A17_DIV_SHIFT           = 8,
  67         MP_DIV_MASK             = 0xf,
  68         MP_DIV_SHIFT            = 4,
  69         M0_DIV_MASK             = 0xf,
  70         M0_DIV_SHIFT            = 0,
  71
  72         /* CLKSEL1: pd bus clk pll sel: codec or general */
  73         PD_BUS_SEL_PLL_MASK     = 15,
  74         PD_BUS_SEL_CPLL         = 0,
  75         PD_BUS_SEL_GPLL,
  76
  77         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  78         PD_BUS_PCLK_DIV_SHIFT   = 12,
  79         PD_BUS_PCLK_DIV_MASK    = 7,
  80
  81         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  82         PD_BUS_HCLK_DIV_SHIFT   = 8,
  83         PD_BUS_HCLK_DIV_MASK    = 3,
  84
  85         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  86         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  87         PD_BUS_ACLK_DIV0_MASK   = 0x1f,
  88         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  89         PD_BUS_ACLK_DIV1_MASK   = 0x7,
  90
  91         /*
  92          * CLKSEL10
  93          * peripheral bus pclk div:
  94          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
  95          */
  96         PERI_SEL_PLL_MASK        = 1,
  97         PERI_SEL_PLL_SHIFT       = 15,
  98         PERI_SEL_CPLL           = 0,
  99         PERI_SEL_GPLL,
 100
 101         PERI_PCLK_DIV_SHIFT     = 12,
 102         PERI_PCLK_DIV_MASK      = 3,
 103
 104         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 105         PERI_HCLK_DIV_SHIFT     = 8,
 106         PERI_HCLK_DIV_MASK      = 3,
 107
 108         /*
 109          * peripheral bus aclk div:
 110          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 111          */
 112         PERI_ACLK_DIV_SHIFT     = 0,
 113         PERI_ACLK_DIV_MASK      = 0x1f,
 114
 115         SOCSTS_DPLL_LOCK        = 1 << 5,
 116         SOCSTS_APLL_LOCK        = 1 << 6,
 117         SOCSTS_CPLL_LOCK        = 1 << 7,
 118         SOCSTS_GPLL_LOCK        = 1 << 8,
 119         SOCSTS_NPLL_LOCK        = 1 << 9,
 120 };
 121
 122 #define RATE_TO_DIV(input_rate, output_rate) \
 123         ((input_rate) / (output_rate) - 1);
 124
 125 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 126
 127 #define PLL_DIVISORS(hz, _nr, _no) {\
 128         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 129         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 130                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 131                        "divisors on line " __stringify(__LINE__));
 132
 133 /* Keep divisors as low as possible to reduce jitter and power usage */
 134 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 135 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 136 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 137
 138 int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
 139 {
 140         struct udevice *dev;
 141
 142         for (uclass_find_first_device(UCLASS_CLK, &dev);
 143              dev;
 144              uclass_find_next_device(&dev)) {
 145                 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 146
 147                 if (plat->clk_id == clk_id) {
 148                         *devp = dev;
 149                         return device_probe(dev);
 150                 }
 151         }
 152
 153         return -ENODEV;
 154 }
 155
 156 void *rockchip_get_cru(void)
 157 {
 158         struct rk3288_clk_priv *priv;
 159         struct udevice *dev;
 160         int ret;
 161
 162         ret = rkclk_get_clk(CLK_GENERAL, &dev);
 163         if (ret)
 164                 return ERR_PTR(ret);
 165         priv = dev_get_priv(dev);
 166         return priv->cru;
 167 }
 168
 169 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 170                          const struct pll_div *div)
 171 {
 172         int pll_id = rk_pll_id(clk_id);
 173         struct rk3288_pll *pll = &cru->pll[pll_id];
 174         /* All PLLs have same VCO and output frequency range restrictions. */
 175         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 176         uint output_hz = vco_hz / div->no;
 177
 178         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 179               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 180         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 181                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 182                (div->no == 1 || !(div->no % 2)));
 183
 184         /* enter reset */
 185         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 186
 187         rk_clrsetreg(&pll->con0,
 188                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
 189                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 190         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 191         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 192
 193         udelay(10);
 194
 195         /* return from reset */
 196         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 197
 198         return 0;
 199 }
 200
 201 static inline unsigned int log2(unsigned int value)
 202 {
 203         return fls(value) - 1;
 204 }
 205
 206 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 207                                unsigned int hz)
 208 {
 209         static const struct pll_div dpll_cfg[] = {
 210                 {.nf = 25, .nr = 2, .no = 1},
 211                 {.nf = 400, .nr = 9, .no = 2},
 212                 {.nf = 500, .nr = 9, .no = 2},
 213                 {.nf = 100, .nr = 3, .no = 1},
 214         };
 215         int cfg;
 216
 217         switch (hz) {
 218         case 300000000:
 219                 cfg = 0;
 220                 break;
 221         case 533000000: /* actually 533.3P MHz */
 222                 cfg = 1;
 223                 break;
 224         case 666000000: /* actually 666.6P MHz */
 225                 cfg = 2;
 226                 break;
 227         case 800000000:
 228                 cfg = 3;
 229                 break;
 230         default:
 231                 debug("Unsupported SDRAM frequency");
 232                 return -EINVAL;
 233         }
 234
 235         /* pll enter slow-mode */
 236         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 237                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 238
 239         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 240
 241         /* wait for pll lock */
 242         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 243                 udelay(1);
 244
 245         /* PLL enter normal-mode */
 246         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 247                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 248
 249         return 0;
 250 }
 251
 252 #ifndef CONFIG_SPL_BUILD
 253 #define VCO_MAX_KHZ     2200000
 254 #define VCO_MIN_KHZ     440000
 255 #define FREF_MAX_KHZ    2200000
 256 #define FREF_MIN_KHZ    269
 257
 258 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 259 {
 260         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 261         uint fref_khz;
 262         uint diff_khz, best_diff_khz;
 263         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 264         uint vco_khz;
 265         uint no = 1;
 266         uint freq_khz = freq_hz / 1000;
 267
 268         if (!freq_hz) {
 269                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 270                 return -EINVAL;
 271         }
 272
 273         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 274         if (ext_div) {
 275                 *ext_div = DIV_ROUND_UP(no, max_no);
 276                 no = DIV_ROUND_UP(no, *ext_div);
 277         }
 278
 279         /* only even divisors (and 1) are supported */
 280         if (no > 1)
 281                 no = DIV_ROUND_UP(no, 2) * 2;
 282
 283         vco_khz = freq_khz * no;
 284         if (ext_div)
 285                 vco_khz *= *ext_div;
 286
 287         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 288                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 289                        __func__, freq_hz);
 290                 return -1;
 291         }
 292
 293         div->no = no;
 294
 295         best_diff_khz = vco_khz;
 296         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 297                 fref_khz = ref_khz / nr;
 298                 if (fref_khz < FREF_MIN_KHZ)
 299                         break;
 300                 if (fref_khz > FREF_MAX_KHZ)
 301                         continue;
 302
 303                 nf = vco_khz / fref_khz;
 304                 if (nf >= max_nf)
 305                         continue;
 306                 diff_khz = vco_khz - nf * fref_khz;
 307                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 308                         nf++;
 309                         diff_khz = fref_khz - diff_khz;
 310                 }
 311
 312                 if (diff_khz >= best_diff_khz)
 313                         continue;
 314
 315                 best_diff_khz = diff_khz;
 316                 div->nr = nr;
 317                 div->nf = nf;
 318         }
 319
 320         if (best_diff_khz > 4 * 1000) {
 321                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 322                        __func__, freq_hz, best_diff_khz * 1000);
 323                 return -EINVAL;
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 330                                 int periph, unsigned int rate_hz)
 331 {
 332         struct pll_div npll_config = {0};
 333         u32 lcdc_div;
 334         int ret;
 335
 336         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 337         if (ret)
 338                 return ret;
 339
 340         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 341                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 342         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 343
 344         /* waiting for pll lock */
 345         while (1) {
 346                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 347                         break;
 348                 udelay(1);
 349         }
 350
 351         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 352                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 353
 354         /* vop dclk source clk: npll,dclk_div: 1 */
 355         switch (periph) {
 356         case DCLK_VOP0:
 357                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 358                              (lcdc_div - 1) << 8 | 2 << 0);
 359                 break;
 360         case DCLK_VOP1:
 361                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 362                              (lcdc_div - 1) << 8 | 2 << 6);
 363                 break;
 364         }
 365
 366         return 0;
 367 }
 368 #endif
 369
 370 #ifdef CONFIG_SPL_BUILD
 371 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 372 {
 373         u32 aclk_div;
 374         u32 hclk_div;
 375         u32 pclk_div;
 376
 377         /* pll enter slow-mode */
 378         rk_clrsetreg(&cru->cru_mode_con,
 379                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 380                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 381                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 382                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 383
 384         /* init pll */
 385         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 386         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 387
 388         /* waiting for pll lock */
 389         while ((readl(&grf->soc_status[1]) &
 390                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 391                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 392                 udelay(1);
 393
 394         /*
 395          * pd_bus clock pll source selection and
 396          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 397          */
 398         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 399         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 400         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 401         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 402                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 403
 404         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 405         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 406                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 407
 408         rk_clrsetreg(&cru->cru_clksel_con[1],
 409                      PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
 410                      PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
 411                      PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
 412                      PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
 413                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 414                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 415                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 416                      0 << 0);
 417
 418         /*
 419          * peri clock pll source selection and
 420          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 421          */
 422         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 423         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 424
 425         hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 426         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 427                 PERI_ACLK_HZ && (hclk_div < 0x4));
 428
 429         pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 430         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 431                 PERI_ACLK_HZ && (pclk_div < 0x4));
 432
 433         rk_clrsetreg(&cru->cru_clksel_con[10],
 434                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
 435                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
 436                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
 437                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 438                      pclk_div << PERI_PCLK_DIV_SHIFT |
 439                      hclk_div << PERI_HCLK_DIV_SHIFT |
 440                      aclk_div << PERI_ACLK_DIV_SHIFT);
 441
 442         /* PLL enter normal-mode */
 443         rk_clrsetreg(&cru->cru_mode_con,
 444                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 445                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 446                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 447                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 448 }
 449 #endif
 450
 451 void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 452 {
 453         /* pll enter slow-mode */
 454         rk_clrsetreg(&cru->cru_mode_con,
 455                      APLL_MODE_MASK << APLL_MODE_SHIFT,
 456                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 457
 458         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 459
 460         /* waiting for pll lock */
 461         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 462                 udelay(1);
 463
 464         /*
 465          * core clock pll source selection and
 466          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 467          * core clock select apll, apll clk = 1800MHz
 468          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 469          */
 470         rk_clrsetreg(&cru->cru_clksel_con[0],
 471                      CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
 472                      A17_DIV_MASK << A17_DIV_SHIFT |
 473                      MP_DIV_MASK << MP_DIV_SHIFT |
 474                      M0_DIV_MASK << M0_DIV_SHIFT,
 475                      0 << A17_DIV_SHIFT |
 476                      3 << MP_DIV_SHIFT |
 477                      1 << M0_DIV_SHIFT);
 478
 479         /*
 480          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 481          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 482          */
 483         rk_clrsetreg(&cru->cru_clksel_con[37],
 484                      CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
 485                      ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
 486                      PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
 487                      1 << CLK_L2RAM_DIV_SHIFT |
 488                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 489                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 490
 491         /* PLL enter normal-mode */
 492         rk_clrsetreg(&cru->cru_mode_con,
 493                      APLL_MODE_MASK << APLL_MODE_SHIFT,
 494                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 495 }
 496
 497 /* Get pll rate by id */
 498 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 499                                    enum rk_clk_id clk_id)
 500 {
 501         uint32_t nr, no, nf;
 502         uint32_t con;
 503         int pll_id = rk_pll_id(clk_id);
 504         struct rk3288_pll *pll = &cru->pll[pll_id];
 505         static u8 clk_shift[CLK_COUNT] = {
 506                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 507                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 508         };
 509         uint shift;
 510
 511         con = readl(&cru->cru_mode_con);
 512         shift = clk_shift[clk_id];
 513         switch ((con >> shift) & APLL_MODE_MASK) {
 514         case APLL_MODE_SLOW:
 515                 return OSC_HZ;
 516         case APLL_MODE_NORMAL:
 517                 /* normal mode */
 518                 con = readl(&pll->con0);
 519                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
 520                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
 521                 con = readl(&pll->con1);
 522                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
 523
 524                 return (24 * nf / (nr * no)) * 1000000;
 525         case APLL_MODE_DEEP:
 526         default:
 527                 return 32768;
 528         }
 529 }
 530
 531 static ulong rk3288_clk_get_rate(struct udevice *dev)
 532 {
 533         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 534         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 535
 536         debug("%s\n", dev->name);
 537         return rkclk_pll_get_rate(priv->cru, plat->clk_id);
 538 }
 539
 540 static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
 541 {
 542         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 543         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 544
 545         debug("%s\n", dev->name);
 546         switch (plat->clk_id) {
 547         case CLK_DDR:
 548                 rkclk_configure_ddr(priv->cru, priv->grf, rate);
 549                 break;
 550         default:
 551                 return -ENOENT;
 552         }
 553
 554         return 0;
 555 }
 556
 557 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 558                                   int periph)
 559 {
 560         uint src_rate;
 561         uint div, mux;
 562         u32 con;
 563
 564         switch (periph) {
 565         case HCLK_EMMC:
 566                 con = readl(&cru->cru_clksel_con[12]);
 567                 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 568                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 569                 break;
 570         case HCLK_SDMMC:
 571                 con = readl(&cru->cru_clksel_con[11]);
 572                 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 573                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 574                 break;
 575         case HCLK_SDIO0:
 576                 con = readl(&cru->cru_clksel_con[12]);
 577                 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
 578                 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
 579                 break;
 580         default:
 581                 return -EINVAL;
 582         }
 583
 584         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 585         return DIV_TO_RATE(src_rate, div);
 586 }
 587
 588 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 589                                   int  periph, uint freq)
 590 {
 591         int src_clk_div;
 592         int mux;
 593
 594         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 595         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 596
 597         if (src_clk_div > 0x3f) {
 598                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
 599                 mux = EMMC_PLL_SELECT_24MHZ;
 600                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 601                        (int)MMC0_PLL_SELECT_24MHZ);
 602         } else {
 603                 mux = EMMC_PLL_SELECT_GENERAL;
 604                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 605                        (int)MMC0_PLL_SELECT_GENERAL);
 606         }
 607         switch (periph) {
 608         case HCLK_EMMC:
 609                 rk_clrsetreg(&cru->cru_clksel_con[12],
 610                              EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 611                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 612                              mux << EMMC_PLL_SHIFT |
 613                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 614                 break;
 615         case HCLK_SDMMC:
 616                 rk_clrsetreg(&cru->cru_clksel_con[11],
 617                              MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 618                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 619                              mux << MMC0_PLL_SHIFT |
 620                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 621                 break;
 622         case HCLK_SDIO0:
 623                 rk_clrsetreg(&cru->cru_clksel_con[12],
 624                              SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
 625                              SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
 626                              mux << SDIO0_PLL_SHIFT |
 627                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 628                 break;
 629         default:
 630                 return -EINVAL;
 631         }
 632
 633         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 634 }
 635
 636 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 637                                   int periph)
 638 {
 639         uint div, mux;
 640         u32 con;
 641
 642         switch (periph) {
 643         case SCLK_SPI0:
 644                 con = readl(&cru->cru_clksel_con[25]);
 645                 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
 646                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
 647                 break;
 648         case SCLK_SPI1:
 649                 con = readl(&cru->cru_clksel_con[25]);
 650                 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
 651                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 652                 break;
 653         case SCLK_SPI2:
 654                 con = readl(&cru->cru_clksel_con[39]);
 655                 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
 656                 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
 657                 break;
 658         default:
 659                 return -EINVAL;
 660         }
 661         assert(mux == SPI0_PLL_SELECT_GENERAL);
 662
 663         return DIV_TO_RATE(gclk_rate, div);
 664 }
 665
 666 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 667                                   int periph, uint freq)
 668 {
 669         int src_clk_div;
 670
 671         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 672         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 673         switch (periph) {
 674         case SCLK_SPI0:
 675                 rk_clrsetreg(&cru->cru_clksel_con[25],
 676                              SPI0_PLL_MASK << SPI0_PLL_SHIFT |
 677                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
 678                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 679                              src_clk_div << SPI0_DIV_SHIFT);
 680                 break;
 681         case SCLK_SPI1:
 682                 rk_clrsetreg(&cru->cru_clksel_con[25],
 683                              SPI1_PLL_MASK << SPI1_PLL_SHIFT |
 684                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
 685                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 686                              src_clk_div << SPI1_DIV_SHIFT);
 687                 break;
 688         case SCLK_SPI2:
 689                 rk_clrsetreg(&cru->cru_clksel_con[39],
 690                              SPI2_PLL_MASK << SPI2_PLL_SHIFT |
 691                              SPI2_DIV_MASK << SPI2_DIV_SHIFT,
 692                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 693                              src_clk_div << SPI2_DIV_SHIFT);
 694                 break;
 695         default:
 696                 return -EINVAL;
 697         }
 698
 699         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 700 }
 701
 702 static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
 703 {
 704         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 705         struct udevice *gclk;
 706         ulong new_rate, gclk_rate;
 707         int ret;
 708
 709         ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 710         if (ret)
 711                 return ret;
 712         gclk_rate = clk_get_rate(gclk);
 713         switch (periph) {
 714         case HCLK_EMMC:
 715         case HCLK_SDMMC:
 716         case HCLK_SDIO0:
 717                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
 718                 break;
 719         case SCLK_SPI0:
 720         case SCLK_SPI1:
 721         case SCLK_SPI2:
 722                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
 723                 break;
 724         case PCLK_I2C0:
 725         case PCLK_I2C1:
 726         case PCLK_I2C2:
 727         case PCLK_I2C3:
 728         case PCLK_I2C4:
 729         case PCLK_I2C5:
 730                 return gclk_rate;
 731         default:
 732                 return -ENOENT;
 733         }
 734
 735         return new_rate;
 736 }
 737
 738 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 739 {
 740         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 741         struct rk3288_cru *cru = priv->cru;
 742         struct udevice *gclk;
 743         ulong new_rate, gclk_rate;
 744         int ret;
 745
 746         ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 747         if (ret)
 748                 return ret;
 749         gclk_rate = clk_get_rate(gclk);
 750         switch (periph) {
 751         case HCLK_EMMC:
 752         case HCLK_SDMMC:
 753         case HCLK_SDIO0:
 754                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
 755                 break;
 756         case SCLK_SPI0:
 757         case SCLK_SPI1:
 758         case SCLK_SPI2:
 759                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
 760                 break;
 761 #ifndef CONFIG_SPL_BUILD
 762         case DCLK_VOP0:
 763         case DCLK_VOP1:
 764                 new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
 765                 break;
 766         case SCLK_EDP_24M:
 767                 /* clk_edp_24M source: 24M */
 768                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 769
 770                 /* rst edp */
 771                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 772                 udelay(1);
 773                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 774                 new_rate = rate;
 775                 break;
 776         case ACLK_VOP0:
 777         case ACLK_VOP1: {
 778                 u32 div;
 779
 780                 /* vop aclk source clk: cpll */
 781                 div = CPLL_HZ / rate;
 782                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 783
 784                 switch (periph) {
 785                 case ACLK_VOP0:
 786                         rk_clrsetreg(&cru->cru_clksel_con[31],
 787                                      3 << 6 | 0x1f << 0,
 788                                      0 << 6 | (div - 1) << 0);
 789                         break;
 790                 case ACLK_VOP1:
 791                         rk_clrsetreg(&cru->cru_clksel_con[31],
 792                                      3 << 14 | 0x1f << 8,
 793                                      0 << 14 | (div - 1) << 8);
 794                         break;
 795                 }
 796                 new_rate = rate;
 797                 break;
 798         }
 799         case PCLK_HDMI_CTRL:
 800                 /* enable pclk hdmi ctrl */
 801                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 802
 803                 /* software reset hdmi */
 804                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 805                 udelay(1);
 806                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 807                 new_rate = rate;
 808                 break;
 809 #endif
 810         default:
 811                 return -ENOENT;
 812         }
 813
 814         return new_rate;
 815 }
 816
 817 static struct clk_ops rk3288_clk_ops = {
 818         .get_rate       = rk3288_clk_get_rate,
 819         .set_rate       = rk3288_clk_set_rate,
 820         .set_periph_rate = rk3288_set_periph_rate,
 821         .get_periph_rate = rk3288_get_periph_rate,
 822 };
 823
 824 static int rk3288_clk_probe(struct udevice *dev)
 825 {
 826         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 827         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 828
 829         if (plat->clk_id != CLK_OSC) {
 830                 struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
 831
 832                 priv->cru = parent_priv->cru;
 833                 priv->grf = parent_priv->grf;
 834                 return 0;
 835         }
 836         priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
 837         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 838 #ifdef CONFIG_SPL_BUILD
 839         rkclk_init(priv->cru, priv->grf);
 840 #endif
 841
 842         return 0;
 843 }
 844
 845 static const char *const clk_name[CLK_COUNT] = {
 846         "osc",
 847         "apll",
 848         "dpll",
 849         "cpll",
 850         "gpll",
 851         "npll",
 852 };
 853
 854 static int rk3288_clk_bind(struct udevice *dev)
 855 {
 856         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 857         int pll, ret;
 858
 859         /* We only need to set up the root clock */
 860         if (dev->of_offset == -1) {
 861                 plat->clk_id = CLK_OSC;
 862                 return 0;
 863         }
 864
 865         /* Create devices for P main clocks */
 866         for (pll = 1; pll < CLK_COUNT; pll++) {
 867                 struct udevice *child;
 868                 struct rk3288_clk_plat *cplat;
 869
 870                 debug("%s %s\n", __func__, clk_name[pll]);
 871                 ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
 872                                          &child);
 873                 if (ret)
 874                         return ret;
 875                 cplat = dev_get_platdata(child);
 876                 cplat->clk_id = pll;
 877         }
 878
 879         /* The reset driver does not have a device node, so bind it here */
 880         ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
 881         if (ret)
 882                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 883
 884         return 0;
 885 }
 886
 887 static const struct udevice_id rk3288_clk_ids[] = {
 888         { .compatible = "rockchip,rk3288-cru" },
 889         { }
 890 };
 891
 892 U_BOOT_DRIVER(clk_rk3288) = {
 893         .name           = "clk_rk3288",
 894         .id             = UCLASS_CLK,
 895         .of_match       = rk3288_clk_ids,
 896         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 897         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 898         .ops            = &rk3288_clk_ops,
 899         .bind           = rk3288_clk_bind,
 900         .probe          = rk3288_clk_probe,
 901 };