1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 - BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 #include <asm/arch/clock-axg.h>
11 #include <clk-uclass.h>
16 #include <dt-bindings/clock/axg-clkc.h>
17 #include "clk_meson.h"
19 #define XTAL_RATE 24000000
25 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
27 static struct meson_gate gates[] = {
28 /* Everything Else (EE) domain gates */
29 MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
30 MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
31 MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
32 MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 15),
33 MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
34 MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
35 MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
36 MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
38 /* Always On (AO) domain gates */
39 MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
42 /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
43 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
44 /* CLKID_CLK81 is critical for the system */
46 /* Peripheral Gates */
47 MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
48 MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
51 static int meson_set_gate(struct clk *clk, bool on)
53 struct meson_clk *priv = dev_get_priv(clk->dev);
54 struct meson_gate *gate;
56 if (clk->id >= ARRAY_SIZE(gates))
59 gate = &gates[clk->id];
64 regmap_update_bits(priv->map, gate->reg,
65 BIT(gate->bit), on ? BIT(gate->bit) : 0);
70 static int meson_clk_enable(struct clk *clk)
72 return meson_set_gate(clk, true);
75 static int meson_clk_disable(struct clk *clk)
77 return meson_set_gate(clk, false);
80 static unsigned long meson_clk81_get_rate(struct clk *clk)
82 struct meson_clk *priv = dev_get_priv(clk->dev);
83 unsigned long parent_rate;
97 regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
98 reg = (reg >> 12) & 7;
102 parent_rate = XTAL_RATE;
107 parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
111 regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
112 reg = reg & ((1 << 7) - 1);
114 return parent_rate / reg;
117 static long mpll_rate_from_params(unsigned long parent_rate,
121 unsigned long divisor = (SDM_DEN * n2) + sdm;
126 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
129 static struct parm meson_mpll0_parm[3] = {
130 {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
131 {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
134 static struct parm meson_mpll1_parm[3] = {
135 {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
136 {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
139 static struct parm meson_mpll2_parm[3] = {
140 {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
141 {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
145 * MultiPhase Locked Loops are outputs from a PLL with additional frequency
146 * scaling capabilities. MPLL rates are calculated as:
148 * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
150 static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
152 struct meson_clk *priv = dev_get_priv(clk->dev);
153 struct parm *psdm, *pn2;
154 unsigned long sdm, n2;
155 unsigned long parent_rate;
160 psdm = &meson_mpll0_parm[0];
161 pn2 = &meson_mpll0_parm[1];
164 psdm = &meson_mpll1_parm[0];
165 pn2 = &meson_mpll1_parm[1];
168 psdm = &meson_mpll2_parm[0];
169 pn2 = &meson_mpll2_parm[1];
175 parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
176 if (IS_ERR_VALUE(parent_rate))
179 regmap_read(priv->map, psdm->reg_off, ®);
180 sdm = PARM_GET(psdm->width, psdm->shift, reg);
182 regmap_read(priv->map, pn2->reg_off, ®);
183 n2 = PARM_GET(pn2->width, pn2->shift, reg);
185 return mpll_rate_from_params(parent_rate, sdm, n2);
188 static struct parm meson_fixed_pll_parm[3] = {
189 {HHI_MPLL_CNTL, 0, 9}, /* pm */
190 {HHI_MPLL_CNTL, 9, 5}, /* pn */
191 {HHI_MPLL_CNTL, 16, 2}, /* pod */
194 static struct parm meson_sys_pll_parm[3] = {
195 {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
196 {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
197 {HHI_SYS_PLL_CNTL, 16, 2}, /* pod */
200 static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
202 struct meson_clk *priv = dev_get_priv(clk->dev);
203 struct parm *pm, *pn, *pod;
204 unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
209 case CLKID_FIXED_PLL:
210 pm = &meson_fixed_pll_parm[0];
211 pn = &meson_fixed_pll_parm[1];
212 pod = &meson_fixed_pll_parm[2];
215 pm = &meson_sys_pll_parm[0];
216 pn = &meson_sys_pll_parm[1];
217 pod = &meson_sys_pll_parm[2];
223 regmap_read(priv->map, pn->reg_off, ®);
224 n = PARM_GET(pn->width, pn->shift, reg);
226 regmap_read(priv->map, pm->reg_off, ®);
227 m = PARM_GET(pm->width, pm->shift, reg);
229 regmap_read(priv->map, pod->reg_off, ®);
230 od = PARM_GET(pod->width, pod->shift, reg);
232 return ((parent_rate_mhz * m / n) >> od) * 1000000;
235 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
240 case CLKID_FIXED_PLL:
242 rate = meson_pll_get_rate(clk, id);
244 case CLKID_FCLK_DIV2:
245 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
247 case CLKID_FCLK_DIV3:
248 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
250 case CLKID_FCLK_DIV4:
251 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
253 case CLKID_FCLK_DIV5:
254 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
256 case CLKID_FCLK_DIV7:
257 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
262 rate = meson_mpll_get_rate(clk, id);
265 rate = meson_clk81_get_rate(clk);
268 if (gates[id].reg != 0) {
270 rate = meson_clk81_get_rate(clk);
276 debug("clock %lu has rate %lu\n", id, rate);
280 static ulong meson_clk_get_rate(struct clk *clk)
282 return meson_clk_get_rate_by_id(clk, clk->id);
285 static int meson_clk_probe(struct udevice *dev)
287 struct meson_clk *priv = dev_get_priv(dev);
289 priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
290 if (IS_ERR(priv->map))
291 return PTR_ERR(priv->map);
293 debug("meson-clk-axg: probed\n");
298 static struct clk_ops meson_clk_ops = {
299 .disable = meson_clk_disable,
300 .enable = meson_clk_enable,
301 .get_rate = meson_clk_get_rate,
304 static const struct udevice_id meson_clk_ids[] = {
305 { .compatible = "amlogic,axg-clkc" },
309 U_BOOT_DRIVER(meson_clk_axg) = {
310 .name = "meson_clk_axg",
312 .of_match = meson_clk_ids,
313 .priv_auto_alloc_size = sizeof(struct meson_clk),
314 .ops = &meson_clk_ops,
315 .probe = meson_clk_probe,