1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
7 #include <clk-uclass.h>
10 struct clk_fixed_rate {
12 unsigned long fixed_rate;
15 #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
17 static ulong clk_fixed_rate_get_rate(struct clk *clk)
19 return to_clk_fixed_rate(clk->dev)->fixed_rate;
22 const struct clk_ops clk_fixed_rate_ops = {
23 .get_rate = clk_fixed_rate_get_rate,
26 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
28 struct clk *clk = &to_clk_fixed_rate(dev)->clk;
29 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
30 to_clk_fixed_rate(dev)->fixed_rate =
31 dev_read_u32_default(dev, "clock-frequency", 0);
33 /* Make fixed rate clock accessible from higher level struct clk */
34 dev->uclass_priv = clk;
40 static const struct udevice_id clk_fixed_rate_match[] = {
42 .compatible = "fixed-clock",
47 U_BOOT_DRIVER(clk_fixed_rate) = {
48 .name = "fixed_rate_clock",
50 .of_match = clk_fixed_rate_match,
51 .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
52 .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
53 .ops = &clk_fixed_rate_ops,