1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 * Copyright (c) 2016, NVIDIA CORPORATION.
6 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
11 #include <clk-uclass.h>
14 #include <dt-structs.h>
17 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
19 return (const struct clk_ops *)dev->driver->ops;
22 #if CONFIG_IS_ENABLED(OF_CONTROL)
23 # if CONFIG_IS_ENABLED(OF_PLATDATA)
24 int clk_get_by_index_platdata(struct udevice *dev, int index,
25 struct phandle_1_arg *cells, struct clk *clk)
31 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
34 clk->id = cells[0].arg[0];
39 static int clk_of_xlate_default(struct clk *clk,
40 struct ofnode_phandle_args *args)
42 debug("%s(clk=%p)\n", __func__, clk);
44 if (args->args_count > 1) {
45 debug("Invaild args_count: %d\n", args->args_count);
50 clk->id = args->args[0];
59 static int clk_get_by_index_tail(int ret, ofnode node,
60 struct ofnode_phandle_args *args,
61 const char *list_name, int index,
64 struct udevice *dev_clk;
65 const struct clk_ops *ops;
72 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
74 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
81 ops = clk_dev_ops(dev_clk);
84 ret = ops->of_xlate(clk, args);
86 ret = clk_of_xlate_default(clk, args);
88 debug("of_xlate() failed: %d\n", ret);
92 return clk_request(dev_clk, clk);
94 debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
95 __func__, ofnode_get_name(node), list_name, index, ret);
99 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
100 int index, struct clk *clk)
103 struct ofnode_phandle_args args;
105 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
110 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
113 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
119 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
123 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
125 struct ofnode_phandle_args args;
128 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
131 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
135 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
137 struct ofnode_phandle_args args;
140 ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
143 return clk_get_by_index_tail(ret, node, &args, "clocks",
147 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
149 int i, ret, err, count;
153 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
157 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
161 for (i = 0; i < count; i++) {
162 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
172 err = clk_release_all(bulk->clks, bulk->count);
174 debug("%s: could release all clocks for %p\n",
180 static int clk_set_default_parents(struct udevice *dev)
182 struct clk clk, parent_clk;
187 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
189 if (num_parents < 0) {
190 debug("%s: could not read assigned-clock-parents for %p\n",
195 for (index = 0; index < num_parents; index++) {
196 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
198 /* If -ENOENT, this is a no-op entry */
203 debug("%s: could not get parent clock %d for %s\n",
204 __func__, index, dev_read_name(dev));
208 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
211 debug("%s: could not get assigned clock %d for %s\n",
212 __func__, index, dev_read_name(dev));
216 ret = clk_set_parent(&clk, &parent_clk);
219 * Not all drivers may support clock-reparenting (as of now).
220 * Ignore errors due to this.
226 debug("%s: failed to reparent clock %d for %s\n",
227 __func__, index, dev_read_name(dev));
235 static int clk_set_default_rates(struct udevice *dev)
244 size = dev_read_size(dev, "assigned-clock-rates");
248 num_rates = size / sizeof(u32);
249 rates = calloc(num_rates, sizeof(u32));
253 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
257 for (index = 0; index < num_rates; index++) {
258 /* If 0 is passed, this is a no-op */
262 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
265 debug("%s: could not get assigned clock %d for %s\n",
266 __func__, index, dev_read_name(dev));
270 ret = clk_set_rate(&clk, rates[index]);
272 debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
273 __func__, index, clk.id, dev_read_name(dev));
283 int clk_set_defaults(struct udevice *dev)
287 /* If this not in SPL and pre-reloc state, don't take any action. */
288 if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
291 debug("%s(%s)\n", __func__, dev_read_name(dev));
293 ret = clk_set_default_parents(dev);
297 ret = clk_set_default_rates(dev);
303 # endif /* OF_PLATDATA */
305 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
309 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
312 index = dev_read_stringlist_search(dev, "clock-names", name);
314 debug("fdt_stringlist_search() failed: %d\n", index);
318 return clk_get_by_index(dev, index, clk);
321 int clk_release_all(struct clk *clk, int count)
325 for (i = 0; i < count; i++) {
326 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
328 /* check if clock has been previously requested */
332 ret = clk_disable(&clk[i]);
333 if (ret && ret != -ENOSYS)
336 ret = clk_free(&clk[i]);
337 if (ret && ret != -ENOSYS)
344 #endif /* OF_CONTROL */
346 int clk_request(struct udevice *dev, struct clk *clk)
348 const struct clk_ops *ops = clk_dev_ops(dev);
350 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
357 return ops->request(clk);
360 int clk_free(struct clk *clk)
362 const struct clk_ops *ops = clk_dev_ops(clk->dev);
364 debug("%s(clk=%p)\n", __func__, clk);
369 return ops->free(clk);
372 ulong clk_get_rate(struct clk *clk)
374 const struct clk_ops *ops = clk_dev_ops(clk->dev);
376 debug("%s(clk=%p)\n", __func__, clk);
381 return ops->get_rate(clk);
384 ulong clk_set_rate(struct clk *clk, ulong rate)
386 const struct clk_ops *ops = clk_dev_ops(clk->dev);
388 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
393 return ops->set_rate(clk, rate);
396 int clk_set_parent(struct clk *clk, struct clk *parent)
398 const struct clk_ops *ops = clk_dev_ops(clk->dev);
400 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
402 if (!ops->set_parent)
405 return ops->set_parent(clk, parent);
408 int clk_enable(struct clk *clk)
410 const struct clk_ops *ops = clk_dev_ops(clk->dev);
412 debug("%s(clk=%p)\n", __func__, clk);
417 return ops->enable(clk);
420 int clk_enable_bulk(struct clk_bulk *bulk)
424 for (i = 0; i < bulk->count; i++) {
425 ret = clk_enable(&bulk->clks[i]);
426 if (ret < 0 && ret != -ENOSYS)
433 int clk_disable(struct clk *clk)
435 const struct clk_ops *ops = clk_dev_ops(clk->dev);
437 debug("%s(clk=%p)\n", __func__, clk);
442 return ops->disable(clk);
445 int clk_disable_bulk(struct clk_bulk *bulk)
449 for (i = 0; i < bulk->count; i++) {
450 ret = clk_disable(&bulk->clks[i]);
451 if (ret < 0 && ret != -ENOSYS)
458 UCLASS_DRIVER(clk) = {