1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 * Copyright (c) 2016, NVIDIA CORPORATION.
6 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
11 #include <clk-uclass.h>
14 #include <dt-structs.h>
16 #include <linux/clk-provider.h>
18 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
20 return (const struct clk_ops *)dev->driver->ops;
23 #if CONFIG_IS_ENABLED(OF_CONTROL)
24 # if CONFIG_IS_ENABLED(OF_PLATDATA)
25 int clk_get_by_index_platdata(struct udevice *dev, int index,
26 struct phandle_1_arg *cells, struct clk *clk)
32 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
35 clk->id = cells[0].arg[0];
40 static int clk_of_xlate_default(struct clk *clk,
41 struct ofnode_phandle_args *args)
43 debug("%s(clk=%p)\n", __func__, clk);
45 if (args->args_count > 1) {
46 debug("Invaild args_count: %d\n", args->args_count);
51 clk->id = args->args[0];
58 static int clk_get_by_index_tail(int ret, ofnode node,
59 struct ofnode_phandle_args *args,
60 const char *list_name, int index,
63 struct udevice *dev_clk;
64 const struct clk_ops *ops;
71 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
73 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
80 ops = clk_dev_ops(dev_clk);
83 ret = ops->of_xlate(clk, args);
85 ret = clk_of_xlate_default(clk, args);
87 debug("of_xlate() failed: %d\n", ret);
91 return clk_request(dev_clk, clk);
93 debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
94 __func__, ofnode_get_name(node), list_name, index, ret);
98 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
99 int index, struct clk *clk)
102 struct ofnode_phandle_args args;
104 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
109 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
112 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
118 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
122 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
124 struct ofnode_phandle_args args;
127 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
130 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
134 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
136 struct ofnode_phandle_args args;
139 ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
142 return clk_get_by_index_tail(ret, node, &args, "clocks",
146 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
148 int i, ret, err, count;
152 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
156 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
160 for (i = 0; i < count; i++) {
161 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
171 err = clk_release_all(bulk->clks, bulk->count);
173 debug("%s: could release all clocks for %p\n",
179 static int clk_set_default_parents(struct udevice *dev)
181 struct clk clk, parent_clk;
186 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
188 if (num_parents < 0) {
189 debug("%s: could not read assigned-clock-parents for %p\n",
194 for (index = 0; index < num_parents; index++) {
195 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
197 /* If -ENOENT, this is a no-op entry */
202 debug("%s: could not get parent clock %d for %s\n",
203 __func__, index, dev_read_name(dev));
207 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
210 debug("%s: could not get assigned clock %d for %s\n",
211 __func__, index, dev_read_name(dev));
215 ret = clk_set_parent(&clk, &parent_clk);
218 * Not all drivers may support clock-reparenting (as of now).
219 * Ignore errors due to this.
225 debug("%s: failed to reparent clock %d for %s\n",
226 __func__, index, dev_read_name(dev));
234 static int clk_set_default_rates(struct udevice *dev)
243 size = dev_read_size(dev, "assigned-clock-rates");
247 num_rates = size / sizeof(u32);
248 rates = calloc(num_rates, sizeof(u32));
252 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
256 for (index = 0; index < num_rates; index++) {
257 /* If 0 is passed, this is a no-op */
261 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
264 debug("%s: could not get assigned clock %d for %s\n",
265 __func__, index, dev_read_name(dev));
269 ret = clk_set_rate(&clk, rates[index]);
271 debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
272 __func__, index, clk.id, dev_read_name(dev));
282 int clk_set_defaults(struct udevice *dev)
286 /* If this not in SPL and pre-reloc state, don't take any action. */
287 if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
290 debug("%s(%s)\n", __func__, dev_read_name(dev));
292 ret = clk_set_default_parents(dev);
296 ret = clk_set_default_rates(dev);
302 # endif /* OF_PLATDATA */
304 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
308 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
311 index = dev_read_stringlist_search(dev, "clock-names", name);
313 debug("fdt_stringlist_search() failed: %d\n", index);
317 return clk_get_by_index(dev, index, clk);
320 int clk_release_all(struct clk *clk, int count)
324 for (i = 0; i < count; i++) {
325 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
327 /* check if clock has been previously requested */
331 ret = clk_disable(&clk[i]);
332 if (ret && ret != -ENOSYS)
335 ret = clk_free(&clk[i]);
336 if (ret && ret != -ENOSYS)
343 #endif /* OF_CONTROL */
345 int clk_request(struct udevice *dev, struct clk *clk)
347 const struct clk_ops *ops = clk_dev_ops(dev);
349 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
356 return ops->request(clk);
359 int clk_free(struct clk *clk)
361 const struct clk_ops *ops = clk_dev_ops(clk->dev);
363 debug("%s(clk=%p)\n", __func__, clk);
368 return ops->free(clk);
371 ulong clk_get_rate(struct clk *clk)
373 const struct clk_ops *ops = clk_dev_ops(clk->dev);
375 debug("%s(clk=%p)\n", __func__, clk);
380 return ops->get_rate(clk);
383 struct clk *clk_get_parent(struct clk *clk)
385 struct udevice *pdev;
388 debug("%s(clk=%p)\n", __func__, clk);
390 pdev = dev_get_parent(clk->dev);
391 pclk = dev_get_clk_ptr(pdev);
393 return ERR_PTR(-ENODEV);
398 ulong clk_set_rate(struct clk *clk, ulong rate)
400 const struct clk_ops *ops = clk_dev_ops(clk->dev);
402 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
407 return ops->set_rate(clk, rate);
410 int clk_set_parent(struct clk *clk, struct clk *parent)
412 const struct clk_ops *ops = clk_dev_ops(clk->dev);
414 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
416 if (!ops->set_parent)
419 return ops->set_parent(clk, parent);
422 int clk_enable(struct clk *clk)
424 const struct clk_ops *ops = clk_dev_ops(clk->dev);
426 debug("%s(clk=%p)\n", __func__, clk);
431 return ops->enable(clk);
434 int clk_enable_bulk(struct clk_bulk *bulk)
438 for (i = 0; i < bulk->count; i++) {
439 ret = clk_enable(&bulk->clks[i]);
440 if (ret < 0 && ret != -ENOSYS)
447 int clk_disable(struct clk *clk)
449 const struct clk_ops *ops = clk_dev_ops(clk->dev);
451 debug("%s(clk=%p)\n", __func__, clk);
456 return ops->disable(clk);
459 int clk_disable_bulk(struct clk_bulk *bulk)
463 for (i = 0; i < bulk->count; i++) {
464 ret = clk_disable(&bulk->clks[i]);
465 if (ret < 0 && ret != -ENOSYS)
472 UCLASS_DRIVER(clk) = {