drivers/clk/clk-uclass.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  * Copyright (c) 2016, NVIDIA CORPORATION.
   6  * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
   7  */
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <clk-uclass.h>
  12 #include <dm.h>
  13 #include <dm/read.h>
  14 #include <dt-structs.h>
  15 #include <errno.h>
  16
  17 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
  18 {
  19         return (const struct clk_ops *)dev->driver->ops;
  20 }
  21
  22 #if CONFIG_IS_ENABLED(OF_CONTROL)
  23 # if CONFIG_IS_ENABLED(OF_PLATDATA)
  24 int clk_get_by_index_platdata(struct udevice *dev, int index,
  25                               struct phandle_1_arg *cells, struct clk *clk)
  26 {
  27         int ret;
  28
  29         if (index != 0)
  30                 return -ENOSYS;
  31         ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
  32         if (ret)
  33                 return ret;
  34         clk->id = cells[0].arg[0];
  35
  36         return 0;
  37 }
  38 # else
  39 static int clk_of_xlate_default(struct clk *clk,
  40                                 struct ofnode_phandle_args *args)
  41 {
  42         debug("%s(clk=%p)\n", __func__, clk);
  43
  44         if (args->args_count > 1) {
  45                 debug("Invaild args_count: %d\n", args->args_count);
  46                 return -EINVAL;
  47         }
  48
  49         if (args->args_count)
  50                 clk->id = args->args[0];
  51         else
  52                 clk->id = 0;
  53
  54         return 0;
  55 }
  56
  57 static int clk_get_by_index_tail(int ret, ofnode node,
  58                                  struct ofnode_phandle_args *args,
  59                                  const char *list_name, int index,
  60                                  struct clk *clk)
  61 {
  62         struct udevice *dev_clk;
  63         const struct clk_ops *ops;
  64
  65         assert(clk);
  66         clk->dev = NULL;
  67         if (ret)
  68                 goto err;
  69
  70         ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
  71         if (ret) {
  72                 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  73                       __func__, ret);
  74                 return ret;
  75         }
  76
  77         clk->dev = dev_clk;
  78
  79         ops = clk_dev_ops(dev_clk);
  80
  81         if (ops->of_xlate)
  82                 ret = ops->of_xlate(clk, args);
  83         else
  84                 ret = clk_of_xlate_default(clk, args);
  85         if (ret) {
  86                 debug("of_xlate() failed: %d\n", ret);
  87                 return ret;
  88         }
  89
  90         return clk_request(dev_clk, clk);
  91 err:
  92         debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
  93               __func__, ofnode_get_name(node), list_name, index, ret);
  94         return ret;
  95 }
  96
  97 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
  98                                    int index, struct clk *clk)
  99 {
 100         int ret;
 101         struct ofnode_phandle_args args;
 102
 103         debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
 104
 105         assert(clk);
 106         clk->dev = NULL;
 107
 108         ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
 109                                          index, &args);
 110         if (ret) {
 111                 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
 112                       __func__, ret);
 113                 return ret;
 114         }
 115
 116
 117         return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
 118                                      index > 0, clk);
 119 }
 120
 121 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 122 {
 123         struct ofnode_phandle_args args;
 124         int ret;
 125
 126         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
 127                                          index, &args);
 128
 129         return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
 130                                      index > 0, clk);
 131 }
 132
 133 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
 134 {
 135         struct ofnode_phandle_args args;
 136         int ret;
 137
 138         ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
 139                                              index > 0, &args);
 140
 141         return clk_get_by_index_tail(ret, node, &args, "clocks",
 142                                      index > 0, clk);
 143 }
 144
 145 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
 146 {
 147         int i, ret, err, count;
 148
 149         bulk->count = 0;
 150
 151         count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
 152         if (count < 1)
 153                 return count;
 154
 155         bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
 156         if (!bulk->clks)
 157                 return -ENOMEM;
 158
 159         for (i = 0; i < count; i++) {
 160                 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
 161                 if (ret < 0)
 162                         goto bulk_get_err;
 163
 164                 ++bulk->count;
 165         }
 166
 167         return 0;
 168
 169 bulk_get_err:
 170         err = clk_release_all(bulk->clks, bulk->count);
 171         if (err)
 172                 debug("%s: could release all clocks for %p\n",
 173                       __func__, dev);
 174
 175         return ret;
 176 }
 177
 178 static int clk_set_default_parents(struct udevice *dev)
 179 {
 180         struct clk clk, parent_clk;
 181         int index;
 182         int num_parents;
 183         int ret;
 184
 185         num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
 186                                                   "#clock-cells");
 187         if (num_parents < 0) {
 188                 debug("%s: could not read assigned-clock-parents for %p\n",
 189                       __func__, dev);
 190                 return 0;
 191         }
 192
 193         for (index = 0; index < num_parents; index++) {
 194                 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
 195                                               index, &parent_clk);
 196                 /* If -ENOENT, this is a no-op entry */
 197                 if (ret == -ENOENT)
 198                         continue;
 199
 200                 if (ret) {
 201                         debug("%s: could not get parent clock %d for %s\n",
 202                               __func__, index, dev_read_name(dev));
 203                         return ret;
 204                 }
 205
 206                 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 207                                               index, &clk);
 208                 if (ret) {
 209                         debug("%s: could not get assigned clock %d for %s\n",
 210                               __func__, index, dev_read_name(dev));
 211                         return ret;
 212                 }
 213
 214                 ret = clk_set_parent(&clk, &parent_clk);
 215
 216                 /*
 217                  * Not all drivers may support clock-reparenting (as of now).
 218                  * Ignore errors due to this.
 219                  */
 220                 if (ret == -ENOSYS)
 221                         continue;
 222
 223                 if (ret) {
 224                         debug("%s: failed to reparent clock %d for %s\n",
 225                               __func__, index, dev_read_name(dev));
 226                         return ret;
 227                 }
 228         }
 229
 230         return 0;
 231 }
 232
 233 static int clk_set_default_rates(struct udevice *dev)
 234 {
 235         struct clk clk;
 236         int index;
 237         int num_rates;
 238         int size;
 239         int ret = 0;
 240         u32 *rates = NULL;
 241
 242         size = dev_read_size(dev, "assigned-clock-rates");
 243         if (size < 0)
 244                 return 0;
 245
 246         num_rates = size / sizeof(u32);
 247         rates = calloc(num_rates, sizeof(u32));
 248         if (!rates)
 249                 return -ENOMEM;
 250
 251         ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
 252         if (ret)
 253                 goto fail;
 254
 255         for (index = 0; index < num_rates; index++) {
 256                 /* If 0 is passed, this is a no-op */
 257                 if (!rates[index])
 258                         continue;
 259
 260                 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 261                                               index, &clk);
 262                 if (ret) {
 263                         debug("%s: could not get assigned clock %d for %s\n",
 264                               __func__, index, dev_read_name(dev));
 265                         continue;
 266                 }
 267
 268                 ret = clk_set_rate(&clk, rates[index]);
 269                 if (ret < 0) {
 270                         debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
 271                               __func__, index, clk.id, dev_read_name(dev));
 272                         break;
 273                 }
 274         }
 275
 276 fail:
 277         free(rates);
 278         return ret;
 279 }
 280
 281 int clk_set_defaults(struct udevice *dev)
 282 {
 283         int ret;
 284
 285         /* If this not in SPL and pre-reloc state, don't take any action. */
 286         if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
 287                 return 0;
 288
 289         debug("%s(%s)\n", __func__, dev_read_name(dev));
 290
 291         ret = clk_set_default_parents(dev);
 292         if (ret)
 293                 return ret;
 294
 295         ret = clk_set_default_rates(dev);
 296         if (ret < 0)
 297                 return ret;
 298
 299         return 0;
 300 }
 301 # endif /* OF_PLATDATA */
 302
 303 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
 304 {
 305         int index;
 306
 307         debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
 308         clk->dev = NULL;
 309
 310         index = dev_read_stringlist_search(dev, "clock-names", name);
 311         if (index < 0) {
 312                 debug("fdt_stringlist_search() failed: %d\n", index);
 313                 return index;
 314         }
 315
 316         return clk_get_by_index(dev, index, clk);
 317 }
 318
 319 int clk_release_all(struct clk *clk, int count)
 320 {
 321         int i, ret;
 322
 323         for (i = 0; i < count; i++) {
 324                 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
 325
 326                 /* check if clock has been previously requested */
 327                 if (!clk[i].dev)
 328                         continue;
 329
 330                 ret = clk_disable(&clk[i]);
 331                 if (ret && ret != -ENOSYS)
 332                         return ret;
 333
 334                 ret = clk_free(&clk[i]);
 335                 if (ret && ret != -ENOSYS)
 336                         return ret;
 337         }
 338
 339         return 0;
 340 }
 341
 342 #endif /* OF_CONTROL */
 343
 344 int clk_request(struct udevice *dev, struct clk *clk)
 345 {
 346         const struct clk_ops *ops = clk_dev_ops(dev);
 347
 348         debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
 349
 350         clk->dev = dev;
 351
 352         if (!ops->request)
 353                 return 0;
 354
 355         return ops->request(clk);
 356 }
 357
 358 int clk_free(struct clk *clk)
 359 {
 360         const struct clk_ops *ops = clk_dev_ops(clk->dev);
 361
 362         debug("%s(clk=%p)\n", __func__, clk);
 363
 364         if (!ops->free)
 365                 return 0;
 366
 367         return ops->free(clk);
 368 }
 369
 370 ulong clk_get_rate(struct clk *clk)
 371 {
 372         const struct clk_ops *ops = clk_dev_ops(clk->dev);
 373
 374         debug("%s(clk=%p)\n", __func__, clk);
 375
 376         if (!ops->get_rate)
 377                 return -ENOSYS;
 378
 379         return ops->get_rate(clk);
 380 }
 381
 382 ulong clk_set_rate(struct clk *clk, ulong rate)
 383 {
 384         const struct clk_ops *ops = clk_dev_ops(clk->dev);
 385
 386         debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
 387
 388         if (!ops->set_rate)
 389                 return -ENOSYS;
 390
 391         return ops->set_rate(clk, rate);
 392 }
 393
 394 int clk_set_parent(struct clk *clk, struct clk *parent)
 395 {
 396         const struct clk_ops *ops = clk_dev_ops(clk->dev);
 397
 398         debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
 399
 400         if (!ops->set_parent)
 401                 return -ENOSYS;
 402
 403         return ops->set_parent(clk, parent);
 404 }
 405
 406 int clk_enable(struct clk *clk)
 407 {
 408         const struct clk_ops *ops = clk_dev_ops(clk->dev);
 409
 410         debug("%s(clk=%p)\n", __func__, clk);
 411
 412         if (!ops->enable)
 413                 return -ENOSYS;
 414
 415         return ops->enable(clk);
 416 }
 417
 418 int clk_enable_bulk(struct clk_bulk *bulk)
 419 {
 420         int i, ret;
 421
 422         for (i = 0; i < bulk->count; i++) {
 423                 ret = clk_enable(&bulk->clks[i]);
 424                 if (ret < 0 && ret != -ENOSYS)
 425                         return ret;
 426         }
 427
 428         return 0;
 429 }
 430
 431 int clk_disable(struct clk *clk)
 432 {
 433         const struct clk_ops *ops = clk_dev_ops(clk->dev);
 434
 435         debug("%s(clk=%p)\n", __func__, clk);
 436
 437         if (!ops->disable)
 438                 return -ENOSYS;
 439
 440         return ops->disable(clk);
 441 }
 442
 443 int clk_disable_bulk(struct clk_bulk *bulk)
 444 {
 445         int i, ret;
 446
 447         for (i = 0; i < bulk->count; i++) {
 448                 ret = clk_disable(&bulk->clks[i]);
 449                 if (ret < 0 && ret != -ENOSYS)
 450                         return ret;
 451         }
 452
 453         return 0;
 454 }
 455
 456 UCLASS_DRIVER(clk) = {
 457         .id             = UCLASS_CLK,
 458         .name           = "clk",
 459 };