1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
8 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 * Simple multiplexer clock implementation
14 * U-Boot CCF porting node:
16 * The Linux kernel - as of tag: 5.0-rc3 is using also the imx_clk_fixup_mux()
17 * version of CCF mux. It is used on e.g. imx6q to provide fixes (like
18 * imx_cscmr1_fixup) for broken HW.
20 * At least for IMX6Q (but NOT IMX6QP) it is important when we set the parent
27 #include <clk-uclass.h>
28 #include <dm/device.h>
29 #include <linux/clk-provider.h>
33 #define UBOOT_DM_CLK_CCF_MUX "ccf_clk_mux"
35 int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
38 struct clk_mux *mux = to_clk_mux(clk);
39 int num_parents = mux->num_parents;
44 for (i = 0; i < num_parents; i++)
50 if (val && (flags & CLK_MUX_INDEX_BIT))
53 if (val && (flags & CLK_MUX_INDEX_ONE))
56 if (val >= num_parents)
62 static u8 clk_mux_get_parent(struct clk *clk)
64 struct clk_mux *mux = to_clk_mux(clk);
67 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
68 val = mux->io_mux_val;
70 val = readl(mux->reg);
75 return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
78 const struct clk_ops clk_mux_ops = {
79 .get_rate = clk_generic_get_rate,
82 struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
83 const char * const *parent_names, u8 num_parents,
85 void __iomem *reg, u8 shift, u32 mask,
86 u8 clk_mux_flags, u32 *table)
93 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
94 width = fls(mask) - ffs(mask) + 1;
95 if (width + shift > 16) {
96 pr_err("mux value exceeds LOWORD field\n");
97 return ERR_PTR(-EINVAL);
101 /* allocate the mux */
102 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
104 return ERR_PTR(-ENOMEM);
106 /* U-boot specific assignments */
107 mux->parent_names = parent_names;
108 mux->num_parents = num_parents;
110 /* struct clk_mux assignments */
114 mux->flags = clk_mux_flags;
116 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
117 mux->io_mux_val = *(u32 *)reg;
123 * Read the current mux setup - so we assign correct parent.
125 * Changing parent would require changing internals of udevice struct
126 * for the corresponding clock (to do that define .set_parent() method.
128 ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
129 parent_names[clk_mux_get_parent(clk)]);
138 struct clk *clk_register_mux_table(struct device *dev, const char *name,
139 const char * const *parent_names, u8 num_parents,
141 void __iomem *reg, u8 shift, u32 mask,
142 u8 clk_mux_flags, u32 *table)
146 clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
147 flags, reg, shift, mask, clk_mux_flags,
150 return ERR_CAST(clk);
154 struct clk *clk_register_mux(struct device *dev, const char *name,
155 const char * const *parent_names, u8 num_parents,
157 void __iomem *reg, u8 shift, u8 width,
160 u32 mask = BIT(width) - 1;
162 return clk_register_mux_table(dev, name, parent_names, num_parents,
163 flags, reg, shift, mask, clk_mux_flags,
167 U_BOOT_DRIVER(ccf_clk_mux) = {
168 .name = UBOOT_DM_CLK_CCF_MUX,
171 .flags = DM_FLAG_PRE_RELOC,