drivers/clk/clk-hsdk-cgu.c

   1 /*
   2  * Synopsys HSDK SDP CGU clock driver
   3  *
   4  * Copyright (C) 2017 Synopsys
   5  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <common.h>
  13 #include <clk-uclass.h>
  14 #include <div64.h>
  15 #include <dm.h>
  16 #include <linux/io.h>
  17 #include <asm/arcregs.h>
  18
  19 #include <dt-bindings/clock/snps,hsdk-cgu.h>
  20
  21 /*
  22  * Synopsys ARC HSDK clock tree.
  23  *
  24  *   ------------------
  25  *   | 33.33 MHz xtal |
  26  *   ------------------
  27  *            |
  28  *            |   -----------
  29  *            |-->| ARC PLL |
  30  *            |   -----------
  31  *            |        |
  32  *            |        |-->|CGU_ARC_IDIV|----------->
  33  *            |        |-->|CREG_CORE_IF_DIV|------->
  34  *            |
  35  *            |   --------------
  36  *            |-->| SYSTEM PLL |
  37  *            |   --------------
  38  *            |        |
  39  *            |        |-->|CGU_SYS_IDIV_APB|------->
  40  *            |        |-->|CGU_SYS_IDIV_AXI|------->
  41  *            |        |-->|CGU_SYS_IDIV_*|--------->
  42  *            |        |-->|CGU_SYS_IDIV_EBI_REF|--->
  43  *            |
  44  *            |   --------------
  45  *            |-->| TUNNEL PLL |
  46  *            |   --------------
  47  *            |        |
  48  *            |        |-->|CGU_TUN_IDIV_TUN|----------->
  49  *            |        |-->|CGU_TUN_IDIV_ROM|----------->
  50  *            |        |-->|CGU_TUN_IDIV_PWM|----------->
  51  *            |
  52  *            |   -----------
  53  *            |-->| DDR PLL |
  54  *                -----------
  55  *                     |
  56  *                     |---------------------------->
  57  *
  58  *   ------------------
  59  *   | 27.00 MHz xtal |
  60  *   ------------------
  61  *            |
  62  *            |   ------------
  63  *            |-->| HDMI PLL |
  64  *                ------------
  65  *                     |
  66  *                     |-->|CGU_HDMI_IDIV_APB|------>
  67  */
  68
  69 #define CGU_ARC_IDIV            0x080
  70 #define CGU_TUN_IDIV_TUN        0x380
  71 #define CGU_TUN_IDIV_ROM        0x390
  72 #define CGU_TUN_IDIV_PWM        0x3A0
  73 #define CGU_TUN_IDIV_TIMER      0x3B0
  74 #define CGU_HDMI_IDIV_APB       0x480
  75 #define CGU_SYS_IDIV_APB        0x180
  76 #define CGU_SYS_IDIV_AXI        0x190
  77 #define CGU_SYS_IDIV_ETH        0x1A0
  78 #define CGU_SYS_IDIV_USB        0x1B0
  79 #define CGU_SYS_IDIV_SDIO       0x1C0
  80 #define CGU_SYS_IDIV_HDMI       0x1D0
  81 #define CGU_SYS_IDIV_GFX_CORE   0x1E0
  82 #define CGU_SYS_IDIV_GFX_DMA    0x1F0
  83 #define CGU_SYS_IDIV_GFX_CFG    0x200
  84 #define CGU_SYS_IDIV_DMAC_CORE  0x210
  85 #define CGU_SYS_IDIV_DMAC_CFG   0x220
  86 #define CGU_SYS_IDIV_SDIO_REF   0x230
  87 #define CGU_SYS_IDIV_SPI_REF    0x240
  88 #define CGU_SYS_IDIV_I2C_REF    0x250
  89 #define CGU_SYS_IDIV_UART_REF   0x260
  90 #define CGU_SYS_IDIV_EBI_REF    0x270
  91
  92 #define CGU_IDIV_MASK           0xFF /* All idiv have 8 significant bits */
  93
  94 #define CGU_ARC_PLL             0x0
  95 #define CGU_SYS_PLL             0x10
  96 #define CGU_DDR_PLL             0x20
  97 #define CGU_TUN_PLL             0x30
  98 #define CGU_HDMI_PLL            0x40
  99
 100 #define CGU_PLL_CTRL            0x000 /* ARC PLL control register */
 101 #define CGU_PLL_STATUS          0x004 /* ARC PLL status register */
 102 #define CGU_PLL_FMEAS           0x008 /* ARC PLL frequency measurement register */
 103 #define CGU_PLL_MON             0x00C /* ARC PLL monitor register */
 104
 105 #define CGU_PLL_CTRL_ODIV_SHIFT         2
 106 #define CGU_PLL_CTRL_IDIV_SHIFT         4
 107 #define CGU_PLL_CTRL_FBDIV_SHIFT        9
 108 #define CGU_PLL_CTRL_BAND_SHIFT         20
 109
 110 #define CGU_PLL_CTRL_ODIV_MASK          GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
 111 #define CGU_PLL_CTRL_IDIV_MASK          GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
 112 #define CGU_PLL_CTRL_FBDIV_MASK         GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
 113
 114 #define CGU_PLL_CTRL_PD                 BIT(0)
 115 #define CGU_PLL_CTRL_BYPASS             BIT(1)
 116
 117 #define CGU_PLL_STATUS_LOCK             BIT(0)
 118 #define CGU_PLL_STATUS_ERR              BIT(1)
 119
 120 #define HSDK_PLL_MAX_LOCK_TIME          100 /* 100 us */
 121
 122 #define CREG_CORE_IF_DIV                0x000 /* ARC CORE interface divider */
 123 #define CORE_IF_CLK_THRESHOLD_HZ        500000000
 124 #define CREG_CORE_IF_CLK_DIV_1          0x0
 125 #define CREG_CORE_IF_CLK_DIV_2          0x1
 126
 127 #define MIN_PLL_RATE                    100000000 /* 100 MHz */
 128 #define PARENT_RATE_33                  33333333 /* fixed clock - xtal */
 129 #define PARENT_RATE_27                  27000000 /* fixed clock - xtal */
 130 #define CGU_MAX_CLOCKS                  27
 131
 132 #define MAX_FREQ_VARIATIONS             6
 133
 134 struct hsdk_idiv_cfg {
 135         const u32 oft;
 136         const u8  val[MAX_FREQ_VARIATIONS];
 137 };
 138
 139 struct hsdk_div_full_cfg {
 140         const u32 clk_rate[MAX_FREQ_VARIATIONS];
 141         const u32 pll_rate[MAX_FREQ_VARIATIONS];
 142         const struct hsdk_idiv_cfg idiv[];
 143 };
 144
 145 static const struct hsdk_div_full_cfg hsdk_4xd_tun_clk_cfg = {
 146         { 25000000,  50000000,  75000000,  100000000, 125000000, 150000000 },
 147         { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 148         { CGU_TUN_IDIV_TUN,     { 24,   12,     8,      6,      6,      4 } },
 149         { CGU_TUN_IDIV_ROM,     { 4,    4,      4,      4,      5,      4 } },
 150         { CGU_TUN_IDIV_PWM,     { 8,    8,      8,      8,      10,     8 } },
 151         { CGU_TUN_IDIV_TIMER,   { 12,   12,     12,     12,     15,     12 } },
 152         { /* last one */ }
 153         }
 154 };
 155
 156 static const struct hsdk_div_full_cfg hsdk_tun_clk_cfg = {
 157         { 25000000,  50000000,  75000000,  100000000, 125000000, 150000000 },
 158         { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 159         { CGU_TUN_IDIV_TUN,     { 24,   12,     8,      6,      6,      4 } },
 160         { CGU_TUN_IDIV_ROM,     { 4,    4,      4,      4,      5,      4 } },
 161         { CGU_TUN_IDIV_PWM,     { 8,    8,      8,      8,      10,     8 } },
 162         { /* last one */ }
 163         }
 164 };
 165
 166 static const struct hsdk_div_full_cfg axi_clk_cfg = {
 167         { 200000000,    400000000,      600000000,      800000000 },
 168         { 800000000,    800000000,      600000000,      800000000 }, {
 169         { CGU_SYS_IDIV_APB,      { 4,   4,      3,      4 } },  /* APB */
 170         { CGU_SYS_IDIV_AXI,      { 4,   2,      1,      1 } },  /* AXI */
 171         { CGU_SYS_IDIV_ETH,      { 2,   2,      2,      2 } },  /* ETH */
 172         { CGU_SYS_IDIV_USB,      { 2,   2,      2,      2 } },  /* USB */
 173         { CGU_SYS_IDIV_SDIO,     { 2,   2,      2,      2 } },  /* SDIO */
 174         { CGU_SYS_IDIV_HDMI,     { 2,   2,      2,      2 } },  /* HDMI */
 175         { CGU_SYS_IDIV_GFX_CORE, { 1,   1,      1,      1 } },  /* GPU-CORE */
 176         { CGU_SYS_IDIV_GFX_DMA,  { 2,   2,      2,      2 } },  /* GPU-DMA */
 177         { CGU_SYS_IDIV_GFX_CFG,  { 4,   4,      3,      4 } },  /* GPU-CFG */
 178         { CGU_SYS_IDIV_DMAC_CORE,{ 2,   2,      2,      2 } },  /* DMAC-CORE */
 179         { CGU_SYS_IDIV_DMAC_CFG, { 4,   4,      3,      4 } },  /* DMAC-CFG */
 180         { CGU_SYS_IDIV_SDIO_REF, { 8,   8,      6,      8 } },  /* SDIO-REF */
 181         { CGU_SYS_IDIV_SPI_REF,  { 24,  24,     18,     24 } }, /* SPI-REF */
 182         { CGU_SYS_IDIV_I2C_REF,  { 4,   4,      3,      4 } },  /* I2C-REF */
 183         { CGU_SYS_IDIV_UART_REF, { 24,  24,     18,     24 } }, /* UART-REF */
 184         { CGU_SYS_IDIV_EBI_REF,  { 16,  16,     12,     16 } }, /* EBI-REF */
 185         { /* last one */ }
 186         }
 187 };
 188
 189 struct hsdk_pll_cfg {
 190         const u32 rate;
 191         const u8  idiv;
 192         const u8  fbdiv;
 193         const u8  odiv;
 194         const u8  band;
 195 };
 196
 197 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
 198         { 100000000,  0, 11, 3, 0 },
 199         { 125000000,  0, 14, 3, 0 },
 200         { 133000000,  0, 15, 3, 0 },
 201         { 150000000,  0, 17, 3, 0 },
 202         { 200000000,  1, 47, 3, 0 },
 203         { 233000000,  1, 27, 2, 0 },
 204         { 300000000,  1, 35, 2, 0 },
 205         { 333000000,  1, 39, 2, 0 },
 206         { 400000000,  1, 47, 2, 0 },
 207         { 500000000,  0, 14, 1, 0 },
 208         { 600000000,  0, 17, 1, 0 },
 209         { 700000000,  0, 20, 1, 0 },
 210         { 750000000,  1, 44, 1, 0 },
 211         { 800000000,  0, 23, 1, 0 },
 212         { 900000000,  1, 26, 0, 0 },
 213         { 1000000000, 1, 29, 0, 0 },
 214         { 1100000000, 1, 32, 0, 0 },
 215         { 1200000000, 1, 35, 0, 0 },
 216         { 1300000000, 1, 38, 0, 0 },
 217         { 1400000000, 1, 41, 0, 0 },
 218         { 1500000000, 1, 44, 0, 0 },
 219         { 1600000000, 1, 47, 0, 0 },
 220         {}
 221 };
 222
 223 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
 224         { 297000000,  0, 21, 2, 0 },
 225         { 540000000,  0, 19, 1, 0 },
 226         { 594000000,  0, 21, 1, 0 },
 227         {}
 228 };
 229
 230 struct hsdk_cgu_domain {
 231         /* PLLs registers */
 232         void __iomem *pll_regs;
 233         /* PLLs special registers */
 234         void __iomem *spec_regs;
 235         /* PLLs devdata */
 236         const struct hsdk_pll_devdata *pll;
 237
 238         /* Dividers registers */
 239         void __iomem *idiv_regs;
 240 };
 241
 242 struct hsdk_cgu_clk {
 243         const struct cgu_clk_map *map;
 244         /* CGU block register */
 245         void __iomem *cgu_regs;
 246         /* CREG block register */
 247         void __iomem *creg_regs;
 248
 249         /* The domain we are working with */
 250         struct hsdk_cgu_domain curr_domain;
 251 };
 252
 253 struct hsdk_pll_devdata {
 254         const u32 parent_rate;
 255         const struct hsdk_pll_cfg *const pll_cfg;
 256         const int (*const update_rate)(struct hsdk_cgu_clk *clk,
 257                                        unsigned long rate,
 258                                        const struct hsdk_pll_cfg *cfg);
 259 };
 260
 261 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
 262                                      const struct hsdk_pll_cfg *);
 263 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
 264                                      const struct hsdk_pll_cfg *);
 265
 266 static const struct hsdk_pll_devdata core_pll_dat = {
 267         .parent_rate = PARENT_RATE_33,
 268         .pll_cfg = asdt_pll_cfg,
 269         .update_rate = hsdk_pll_core_update_rate,
 270 };
 271
 272 static const struct hsdk_pll_devdata sdt_pll_dat = {
 273         .parent_rate = PARENT_RATE_33,
 274         .pll_cfg = asdt_pll_cfg,
 275         .update_rate = hsdk_pll_comm_update_rate,
 276 };
 277
 278 static const struct hsdk_pll_devdata hdmi_pll_dat = {
 279         .parent_rate = PARENT_RATE_27,
 280         .pll_cfg = hdmi_pll_cfg,
 281         .update_rate = hsdk_pll_comm_update_rate,
 282 };
 283
 284 static ulong idiv_set(struct clk *, ulong);
 285 static ulong cpu_clk_set(struct clk *, ulong);
 286 static ulong axi_clk_set(struct clk *, ulong);
 287 static ulong tun_hsdk_set(struct clk *, ulong);
 288 static ulong tun_h4xd_set(struct clk *, ulong);
 289 static ulong idiv_get(struct clk *);
 290 static int idiv_off(struct clk *);
 291 static ulong pll_set(struct clk *, ulong);
 292 static ulong pll_get(struct clk *);
 293
 294 struct cgu_clk_map {
 295         const u32 cgu_pll_oft;
 296         const u32 cgu_div_oft;
 297         const struct hsdk_pll_devdata *const pll_devdata;
 298         const ulong (*const get_rate)(struct clk *clk);
 299         const ulong (*const set_rate)(struct clk *clk, ulong rate);
 300         const int (*const disable)(struct clk *clk);
 301 };
 302
 303 static const struct cgu_clk_map hsdk_clk_map[] = {
 304         [CLK_ARC_PLL]        = { CGU_ARC_PLL,  0,                      &core_pll_dat, pll_get,  pll_set,      NULL     },
 305         [CLK_ARC]            = { CGU_ARC_PLL,  CGU_ARC_IDIV,           &core_pll_dat, idiv_get, cpu_clk_set,  idiv_off },
 306         [CLK_DDR_PLL]        = { CGU_DDR_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 307         [CLK_SYS_PLL]        = { CGU_SYS_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 308         [CLK_SYS_APB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_APB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 309         [CLK_SYS_AXI]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_AXI,       &sdt_pll_dat,  idiv_get, axi_clk_set,  idiv_off },
 310         [CLK_SYS_ETH]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_ETH,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 311         [CLK_SYS_USB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_USB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 312         [CLK_SYS_SDIO]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 313         [CLK_SYS_HDMI]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_HDMI,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 314         [CLK_SYS_GFX_CORE]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CORE,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 315         [CLK_SYS_GFX_DMA]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_DMA,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 316         [CLK_SYS_GFX_CFG]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CFG,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 317         [CLK_SYS_DMAC_CORE]  = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 318         [CLK_SYS_DMAC_CFG]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CFG,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 319         [CLK_SYS_SDIO_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 320         [CLK_SYS_SPI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_SPI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 321         [CLK_SYS_I2C_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_I2C_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 322         [CLK_SYS_UART_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_UART_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 323         [CLK_SYS_EBI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_EBI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 324         [CLK_TUN_PLL]        = { CGU_TUN_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 325         [CLK_TUN_TUN]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_TUN,       &sdt_pll_dat,  idiv_get, tun_hsdk_set, idiv_off },
 326         [CLK_TUN_ROM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_ROM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 327         [CLK_TUN_PWM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_PWM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 328         [CLK_TUN_TIMER]      = { /* missing in HSDK */ },
 329         [CLK_HDMI_PLL]       = { CGU_HDMI_PLL, 0,                      &hdmi_pll_dat, pll_get,  pll_set,      NULL     },
 330         [CLK_HDMI]           = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB,      &hdmi_pll_dat, idiv_get, idiv_set,     idiv_off }
 331 };
 332
 333 static const struct cgu_clk_map hsdk_4xd_clk_map[] = {
 334         [CLK_ARC_PLL]        = { CGU_ARC_PLL,  0,                      &core_pll_dat, pll_get,  pll_set,      NULL     },
 335         [CLK_ARC]            = { CGU_ARC_PLL,  CGU_ARC_IDIV,           &core_pll_dat, idiv_get, cpu_clk_set,  idiv_off },
 336         [CLK_DDR_PLL]        = { CGU_DDR_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 337         [CLK_SYS_PLL]        = { CGU_SYS_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 338         [CLK_SYS_APB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_APB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 339         [CLK_SYS_AXI]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_AXI,       &sdt_pll_dat,  idiv_get, axi_clk_set,  idiv_off },
 340         [CLK_SYS_ETH]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_ETH,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 341         [CLK_SYS_USB]        = { CGU_SYS_PLL,  CGU_SYS_IDIV_USB,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 342         [CLK_SYS_SDIO]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 343         [CLK_SYS_HDMI]       = { CGU_SYS_PLL,  CGU_SYS_IDIV_HDMI,      &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 344         [CLK_SYS_GFX_CORE]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_GFX_CORE,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 345         [CLK_SYS_GFX_DMA]    = { /* missing in HSDK-4xD */ },
 346         [CLK_SYS_GFX_CFG]    = { /* missing in HSDK-4xD */ },
 347         [CLK_SYS_DMAC_CORE]  = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 348         [CLK_SYS_DMAC_CFG]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_DMAC_CFG,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 349         [CLK_SYS_SDIO_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_SDIO_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 350         [CLK_SYS_SPI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_SPI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 351         [CLK_SYS_I2C_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_I2C_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 352         [CLK_SYS_UART_REF]   = { CGU_SYS_PLL,  CGU_SYS_IDIV_UART_REF,  &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 353         [CLK_SYS_EBI_REF]    = { CGU_SYS_PLL,  CGU_SYS_IDIV_EBI_REF,   &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 354         [CLK_TUN_PLL]        = { CGU_TUN_PLL,  0,                      &sdt_pll_dat,  pll_get,  pll_set,      NULL     },
 355         [CLK_TUN_TUN]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_TUN,       &sdt_pll_dat,  idiv_get, tun_h4xd_set, idiv_off },
 356         [CLK_TUN_ROM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_ROM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 357         [CLK_TUN_PWM]        = { CGU_TUN_PLL,  CGU_TUN_IDIV_PWM,       &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 358         [CLK_TUN_TIMER]      = { CGU_TUN_PLL,  CGU_TUN_IDIV_TIMER,     &sdt_pll_dat,  idiv_get, idiv_set,     idiv_off },
 359         [CLK_HDMI_PLL]       = { CGU_HDMI_PLL, 0,                      &hdmi_pll_dat, pll_get,  pll_set,      NULL     },
 360         [CLK_HDMI]           = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB,      &hdmi_pll_dat, idiv_get, idiv_set,     idiv_off }
 361 };
 362
 363 static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
 364 {
 365         iowrite32(val, clk->curr_domain.idiv_regs);
 366 }
 367
 368 static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
 369 {
 370         return ioread32(clk->curr_domain.idiv_regs);
 371 }
 372
 373 static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
 374 {
 375         iowrite32(val, clk->curr_domain.pll_regs + reg);
 376 }
 377
 378 static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
 379 {
 380         return ioread32(clk->curr_domain.pll_regs + reg);
 381 }
 382
 383 static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
 384 {
 385         iowrite32(val, clk->curr_domain.spec_regs + reg);
 386 }
 387
 388 static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
 389 {
 390         return ioread32(clk->curr_domain.spec_regs + reg);
 391 }
 392
 393 static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
 394                                     const struct hsdk_pll_cfg *cfg)
 395 {
 396         u32 val = 0;
 397
 398         /* Powerdown and Bypass bits should be cleared */
 399         val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
 400         val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
 401         val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
 402         val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
 403
 404         pr_debug("write configurarion: %#x\n", val);
 405
 406         hsdk_pll_write(clk, CGU_PLL_CTRL, val);
 407 }
 408
 409 static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
 410 {
 411         return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
 412 }
 413
 414 static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
 415 {
 416         return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
 417 }
 418
 419 static ulong pll_get(struct clk *sclk)
 420 {
 421         u32 val;
 422         u64 rate;
 423         u32 idiv, fbdiv, odiv;
 424         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 425         u32 parent_rate = clk->curr_domain.pll->parent_rate;
 426
 427         val = hsdk_pll_read(clk, CGU_PLL_CTRL);
 428
 429         pr_debug("current configurarion: %#x\n", val);
 430
 431         /* Check if PLL is bypassed */
 432         if (val & CGU_PLL_CTRL_BYPASS)
 433                 return parent_rate;
 434
 435         /* Check if PLL is disabled */
 436         if (val & CGU_PLL_CTRL_PD)
 437                 return 0;
 438
 439         /* input divider = reg.idiv + 1 */
 440         idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
 441         /* fb divider = 2*(reg.fbdiv + 1) */
 442         fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
 443         /* output divider = 2^(reg.odiv) */
 444         odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
 445
 446         rate = (u64)parent_rate * fbdiv;
 447         do_div(rate, idiv * odiv);
 448
 449         return rate;
 450 }
 451
 452 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
 453 {
 454         int i;
 455         unsigned long best_rate;
 456         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 457         const struct hsdk_pll_cfg *pll_cfg = clk->curr_domain.pll->pll_cfg;
 458
 459         if (pll_cfg[0].rate == 0)
 460                 return -EINVAL;
 461
 462         best_rate = pll_cfg[0].rate;
 463
 464         for (i = 1; pll_cfg[i].rate != 0; i++) {
 465                 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
 466                         best_rate = pll_cfg[i].rate;
 467         }
 468
 469         pr_debug("chosen best rate: %lu\n", best_rate);
 470
 471         return best_rate;
 472 }
 473
 474 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
 475                                      unsigned long rate,
 476                                      const struct hsdk_pll_cfg *cfg)
 477 {
 478         hsdk_pll_set_cfg(clk, cfg);
 479
 480         /*
 481          * Wait until CGU relocks and check error status.
 482          * If after timeout CGU is unlocked yet return error.
 483          */
 484         udelay(HSDK_PLL_MAX_LOCK_TIME);
 485         if (!hsdk_pll_is_locked(clk))
 486                 return -ETIMEDOUT;
 487
 488         if (hsdk_pll_is_err(clk))
 489                 return -EINVAL;
 490
 491         return 0;
 492 }
 493
 494 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
 495                                      unsigned long rate,
 496                                      const struct hsdk_pll_cfg *cfg)
 497 {
 498         /*
 499          * When core clock exceeds 500MHz, the divider for the interface
 500          * clock must be programmed to div-by-2.
 501          */
 502         if (rate > CORE_IF_CLK_THRESHOLD_HZ)
 503                 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
 504
 505         hsdk_pll_set_cfg(clk, cfg);
 506
 507         /*
 508          * Wait until CGU relocks and check error status.
 509          * If after timeout CGU is unlocked yet return error.
 510          */
 511         udelay(HSDK_PLL_MAX_LOCK_TIME);
 512         if (!hsdk_pll_is_locked(clk))
 513                 return -ETIMEDOUT;
 514
 515         if (hsdk_pll_is_err(clk))
 516                 return -EINVAL;
 517
 518         /*
 519          * Program divider to div-by-1 if we succesfuly set core clock below
 520          * 500MHz threshold.
 521          */
 522         if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
 523                 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
 524
 525         return 0;
 526 }
 527
 528 static ulong pll_set(struct clk *sclk, ulong rate)
 529 {
 530         int i;
 531         unsigned long best_rate;
 532         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 533         const struct hsdk_pll_devdata *pll = clk->curr_domain.pll;
 534         const struct hsdk_pll_cfg *pll_cfg = pll->pll_cfg;
 535
 536         best_rate = hsdk_pll_round_rate(sclk, rate);
 537
 538         for (i = 0; pll_cfg[i].rate != 0; i++)
 539                 if (pll_cfg[i].rate == best_rate)
 540                         return pll->update_rate(clk, best_rate, &pll_cfg[i]);
 541
 542         pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
 543                pll->parent_rate);
 544
 545         return -EINVAL;
 546 }
 547
 548 static int idiv_off(struct clk *sclk)
 549 {
 550         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 551
 552         hsdk_idiv_write(clk, 0);
 553
 554         return 0;
 555 }
 556
 557 static ulong idiv_get(struct clk *sclk)
 558 {
 559         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 560         ulong parent_rate = pll_get(sclk);
 561         u32 div_factor = hsdk_idiv_read(clk);
 562
 563         div_factor &= CGU_IDIV_MASK;
 564
 565         pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
 566
 567         if (div_factor == 0)
 568                 return 0;
 569
 570         return parent_rate / div_factor;
 571 }
 572
 573 /* Special behavior: wen we set this clock we set both idiv and pll */
 574 static ulong cpu_clk_set(struct clk *sclk, ulong rate)
 575 {
 576         ulong ret;
 577
 578         ret = pll_set(sclk, rate);
 579         idiv_set(sclk, rate);
 580
 581         return ret;
 582 }
 583
 584 /*
 585  * Special behavior:
 586  * when we set these clocks we set both PLL and all idiv dividers related to
 587  * this PLL domain.
 588  */
 589 static ulong common_div_clk_set(struct clk *sclk, ulong rate,
 590                                 const struct hsdk_div_full_cfg *cfg)
 591 {
 592         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 593         ulong pll_rate;
 594         int i, freq_idx = -1;
 595         ulong ret = 0;
 596
 597         pll_rate = pll_get(sclk);
 598
 599         for (i = 0; i < MAX_FREQ_VARIATIONS; i++) {
 600                 /* unused freq variations are filled with 0 */
 601                 if (!cfg->clk_rate[i])
 602                         break;
 603
 604                 if (cfg->clk_rate[i] == rate) {
 605                         freq_idx = i;
 606                         break;
 607                 }
 608         }
 609
 610         if (freq_idx < 0) {
 611                 pr_err("clk: invalid rate=%ld Hz\n", rate);
 612                 return -EINVAL;
 613         }
 614
 615         /* configure PLL before dividers */
 616         if (cfg->pll_rate[freq_idx] < pll_rate)
 617                 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
 618
 619         /* configure SYS dividers */
 620         for (i = 0; cfg->idiv[i].oft != 0; i++) {
 621                 clk->curr_domain.idiv_regs = clk->cgu_regs + cfg->idiv[i].oft;
 622                 hsdk_idiv_write(clk, cfg->idiv[i].val[freq_idx]);
 623         }
 624
 625         /* configure PLL after dividers */
 626         if (cfg->pll_rate[freq_idx] >= pll_rate)
 627                 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
 628
 629         return ret;
 630 }
 631
 632 static ulong axi_clk_set(struct clk *sclk, ulong rate)
 633 {
 634         return common_div_clk_set(sclk, rate, &axi_clk_cfg);
 635 }
 636
 637 static ulong tun_hsdk_set(struct clk *sclk, ulong rate)
 638 {
 639         return common_div_clk_set(sclk, rate, &hsdk_tun_clk_cfg);
 640 }
 641
 642 static ulong tun_h4xd_set(struct clk *sclk, ulong rate)
 643 {
 644         return common_div_clk_set(sclk, rate, &hsdk_4xd_tun_clk_cfg);
 645 }
 646
 647 static ulong idiv_set(struct clk *sclk, ulong rate)
 648 {
 649         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 650         ulong parent_rate = pll_get(sclk);
 651         u32 div_factor;
 652
 653         div_factor = parent_rate / rate;
 654         if (abs(rate - parent_rate / (div_factor + 1)) <=
 655             abs(rate - parent_rate / div_factor)) {
 656                 div_factor += 1;
 657         }
 658
 659         if (div_factor & ~CGU_IDIV_MASK) {
 660                 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
 661                        rate, parent_rate, div_factor, CGU_IDIV_MASK);
 662
 663                 div_factor = CGU_IDIV_MASK;
 664         }
 665
 666         if (div_factor == 0) {
 667                 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
 668                        rate, parent_rate, div_factor);
 669
 670                 div_factor = 1;
 671         }
 672
 673         hsdk_idiv_write(clk, div_factor);
 674
 675         return 0;
 676 }
 677
 678 static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
 679 {
 680         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 681
 682         if (sclk->id >= CGU_MAX_CLOCKS)
 683                 return -EINVAL;
 684
 685         /* clocks missing in current map have their entry zeroed */
 686         if (!clk->map[sclk->id].pll_devdata)
 687                 return -EINVAL;
 688
 689         clk->curr_domain.pll = clk->map[sclk->id].pll_devdata;
 690         clk->curr_domain.pll_regs = clk->cgu_regs + clk->map[sclk->id].cgu_pll_oft;
 691         clk->curr_domain.spec_regs = clk->creg_regs;
 692         clk->curr_domain.idiv_regs = clk->cgu_regs + clk->map[sclk->id].cgu_div_oft;
 693
 694         return 0;
 695 }
 696
 697 static ulong hsdk_cgu_get_rate(struct clk *sclk)
 698 {
 699         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 700
 701         if (hsdk_prepare_clock_tree_branch(sclk))
 702                 return -EINVAL;
 703
 704         return clk->map[sclk->id].get_rate(sclk);
 705 }
 706
 707 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
 708 {
 709         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 710
 711         if (hsdk_prepare_clock_tree_branch(sclk))
 712                 return -EINVAL;
 713
 714         if (clk->map[sclk->id].set_rate)
 715                 return clk->map[sclk->id].set_rate(sclk, rate);
 716
 717         return -ENOTSUPP;
 718 }
 719
 720 static int hsdk_cgu_disable(struct clk *sclk)
 721 {
 722         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 723
 724         if (hsdk_prepare_clock_tree_branch(sclk))
 725                 return -EINVAL;
 726
 727         if (clk->map[sclk->id].disable)
 728                 return clk->map[sclk->id].disable(sclk);
 729
 730         return -ENOTSUPP;
 731 }
 732
 733 static const struct clk_ops hsdk_cgu_ops = {
 734         .set_rate = hsdk_cgu_set_rate,
 735         .get_rate = hsdk_cgu_get_rate,
 736         .disable = hsdk_cgu_disable,
 737 };
 738
 739 static int hsdk_cgu_clk_probe(struct udevice *dev)
 740 {
 741         struct hsdk_cgu_clk *hsdk_clk = dev_get_priv(dev);
 742
 743         BUILD_BUG_ON(ARRAY_SIZE(hsdk_clk_map) != CGU_MAX_CLOCKS);
 744         BUILD_BUG_ON(ARRAY_SIZE(hsdk_4xd_clk_map) != CGU_MAX_CLOCKS);
 745
 746         /* Choose which clock map to use in runtime */
 747         if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF) == 0x52)
 748                 hsdk_clk->map = hsdk_clk_map;
 749         else
 750                 hsdk_clk->map = hsdk_4xd_clk_map;
 751
 752         hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
 753         if (!hsdk_clk->cgu_regs)
 754                 return -EINVAL;
 755
 756         hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
 757         if (!hsdk_clk->creg_regs)
 758                 return -EINVAL;
 759
 760         return 0;
 761 }
 762
 763 static const struct udevice_id hsdk_cgu_clk_id[] = {
 764         { .compatible = "snps,hsdk-cgu-clock" },
 765         { }
 766 };
 767
 768 U_BOOT_DRIVER(hsdk_cgu_clk) = {
 769         .name = "hsdk-cgu-clk",
 770         .id = UCLASS_CLK,
 771         .of_match = hsdk_cgu_clk_id,
 772         .probe = hsdk_cgu_clk_probe,
 773         .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
 774         .ops = &hsdk_cgu_ops,
 775 };