drivers/clk/clk-hsdk-cgu.c

   1 /*
   2  * Synopsys HSDK SDP CGU clock driver
   3  *
   4  * Copyright (C) 2017 Synopsys
   5  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <common.h>
  13 #include <clk-uclass.h>
  14 #include <div64.h>
  15 #include <dm.h>
  16 #include <linux/io.h>
  17
  18 /*
  19  * Synopsys ARC HSDK clock tree.
  20  *
  21  *   ------------------
  22  *   | 33.33 MHz xtal |
  23  *   ------------------
  24  *            |
  25  *            |   -----------
  26  *            |-->| ARC PLL |
  27  *            |   -----------
  28  *            |        |
  29  *            |        |-->|CGU_ARC_IDIV|----------->
  30  *            |        |-->|CREG_CORE_IF_DIV|------->
  31  *            |
  32  *            |   --------------
  33  *            |-->| SYSTEM PLL |
  34  *            |   --------------
  35  *            |        |
  36  *            |        |-->|CGU_SYS_IDIV_APB|------->
  37  *            |        |-->|CGU_SYS_IDIV_AXI|------->
  38  *            |        |-->|CGU_SYS_IDIV_*|--------->
  39  *            |        |-->|CGU_SYS_IDIV_EBI_REF|--->
  40  *            |
  41  *            |   --------------
  42  *            |-->| TUNNEL PLL |
  43  *            |   --------------
  44  *            |        |
  45  *            |        |-->|CGU_TUN_IDIV_TUN|----------->
  46  *            |        |-->|CGU_TUN_IDIV_ROM|----------->
  47  *            |        |-->|CGU_TUN_IDIV_PWM|----------->
  48  *            |
  49  *            |   -----------
  50  *            |-->| DDR PLL |
  51  *                -----------
  52  *                     |
  53  *                     |---------------------------->
  54  *
  55  *   ------------------
  56  *   | 27.00 MHz xtal |
  57  *   ------------------
  58  *            |
  59  *            |   ------------
  60  *            |-->| HDMI PLL |
  61  *                ------------
  62  *                     |
  63  *                     |-->|CGU_HDMI_IDIV_APB|------>
  64  */
  65
  66 #define CGU_ARC_IDIV            0x080
  67 #define CGU_TUN_IDIV_TUN        0x380
  68 #define CGU_TUN_IDIV_ROM        0x390
  69 #define CGU_TUN_IDIV_PWM        0x3A0
  70 #define CGU_TUN_IDIV_TIMER      0x3B0
  71 #define CGU_HDMI_IDIV_APB       0x480
  72 #define CGU_SYS_IDIV_APB        0x180
  73 #define CGU_SYS_IDIV_AXI        0x190
  74 #define CGU_SYS_IDIV_ETH        0x1A0
  75 #define CGU_SYS_IDIV_USB        0x1B0
  76 #define CGU_SYS_IDIV_SDIO       0x1C0
  77 #define CGU_SYS_IDIV_HDMI       0x1D0
  78 #define CGU_SYS_IDIV_GFX_CORE   0x1E0
  79 #define CGU_SYS_IDIV_GFX_DMA    0x1F0
  80 #define CGU_SYS_IDIV_GFX_CFG    0x200
  81 #define CGU_SYS_IDIV_DMAC_CORE  0x210
  82 #define CGU_SYS_IDIV_DMAC_CFG   0x220
  83 #define CGU_SYS_IDIV_SDIO_REF   0x230
  84 #define CGU_SYS_IDIV_SPI_REF    0x240
  85 #define CGU_SYS_IDIV_I2C_REF    0x250
  86 #define CGU_SYS_IDIV_UART_REF   0x260
  87 #define CGU_SYS_IDIV_EBI_REF    0x270
  88
  89 #define CGU_IDIV_MASK           0xFF /* All idiv have 8 significant bits */
  90
  91 #define CGU_ARC_PLL             0x0
  92 #define CGU_SYS_PLL             0x10
  93 #define CGU_DDR_PLL             0x20
  94 #define CGU_TUN_PLL             0x30
  95 #define CGU_HDMI_PLL            0x40
  96
  97 #define CGU_PLL_CTRL            0x000 /* ARC PLL control register */
  98 #define CGU_PLL_STATUS          0x004 /* ARC PLL status register */
  99 #define CGU_PLL_FMEAS           0x008 /* ARC PLL frequency measurement register */
 100 #define CGU_PLL_MON             0x00C /* ARC PLL monitor register */
 101
 102 #define CGU_PLL_CTRL_ODIV_SHIFT         2
 103 #define CGU_PLL_CTRL_IDIV_SHIFT         4
 104 #define CGU_PLL_CTRL_FBDIV_SHIFT        9
 105 #define CGU_PLL_CTRL_BAND_SHIFT         20
 106
 107 #define CGU_PLL_CTRL_ODIV_MASK          GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
 108 #define CGU_PLL_CTRL_IDIV_MASK          GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
 109 #define CGU_PLL_CTRL_FBDIV_MASK         GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
 110
 111 #define CGU_PLL_CTRL_PD                 BIT(0)
 112 #define CGU_PLL_CTRL_BYPASS             BIT(1)
 113
 114 #define CGU_PLL_STATUS_LOCK             BIT(0)
 115 #define CGU_PLL_STATUS_ERR              BIT(1)
 116
 117 #define HSDK_PLL_MAX_LOCK_TIME          100 /* 100 us */
 118
 119 #define CREG_CORE_IF_DIV                0x000 /* ARC CORE interface divider */
 120 #define CORE_IF_CLK_THRESHOLD_HZ        500000000
 121 #define CREG_CORE_IF_CLK_DIV_1          0x0
 122 #define CREG_CORE_IF_CLK_DIV_2          0x1
 123
 124 #define MIN_PLL_RATE                    100000000 /* 100 MHz */
 125 #define PARENT_RATE_33                  33333333 /* fixed clock - xtal */
 126 #define PARENT_RATE_27                  27000000 /* fixed clock - xtal */
 127 #define CGU_MAX_CLOCKS                  27
 128
 129 #define MAX_FREQ_VARIATIONS             6
 130
 131 struct hsdk_idiv_cfg {
 132         const u32 oft;
 133         const u8  val[MAX_FREQ_VARIATIONS];
 134 };
 135
 136 struct hsdk_div_full_cfg {
 137         const u32 clk_rate[MAX_FREQ_VARIATIONS];
 138         const u32 pll_rate[MAX_FREQ_VARIATIONS];
 139         const struct hsdk_idiv_cfg idiv[];
 140 };
 141
 142 static const struct hsdk_div_full_cfg tun_clk_cfg = {
 143         { 25000000,  50000000,  75000000,  100000000, 125000000, 150000000 },
 144         { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
 145         { CGU_TUN_IDIV_TUN,     { 24,   12,     8,      6,      6,      4 } },
 146         { CGU_TUN_IDIV_ROM,     { 4,    4,      4,      4,      5,      4 } },
 147         { CGU_TUN_IDIV_PWM,     { 8,    8,      8,      8,      10,     8 } },
 148         { CGU_TUN_IDIV_TIMER,   { 12,   12,     12,     12,     15,     12 } },
 149         { /* last one */ }
 150         }
 151 };
 152
 153 static const struct hsdk_div_full_cfg axi_clk_cfg = {
 154         { 200000000,    400000000,      600000000,      800000000 },
 155         { 800000000,    800000000,      600000000,      800000000 }, {
 156         { CGU_SYS_IDIV_APB,      { 4,   4,      3,      4 } },  /* APB */
 157         { CGU_SYS_IDIV_AXI,      { 4,   2,      1,      1 } },  /* AXI */
 158         { CGU_SYS_IDIV_ETH,      { 2,   2,      2,      2 } },  /* ETH */
 159         { CGU_SYS_IDIV_USB,      { 2,   2,      2,      2 } },  /* USB */
 160         { CGU_SYS_IDIV_SDIO,     { 2,   2,      2,      2 } },  /* SDIO */
 161         { CGU_SYS_IDIV_HDMI,     { 2,   2,      2,      2 } },  /* HDMI */
 162         { CGU_SYS_IDIV_GFX_CORE, { 1,   1,      1,      1 } },  /* GPU-CORE */
 163         { CGU_SYS_IDIV_GFX_DMA,  { 2,   2,      2,      2 } },  /* GPU-DMA */
 164         { CGU_SYS_IDIV_GFX_CFG,  { 4,   4,      3,      4 } },  /* GPU-CFG */
 165         { CGU_SYS_IDIV_DMAC_CORE,{ 2,   2,      2,      2 } },  /* DMAC-CORE */
 166         { CGU_SYS_IDIV_DMAC_CFG, { 4,   4,      3,      4 } },  /* DMAC-CFG */
 167         { CGU_SYS_IDIV_SDIO_REF, { 8,   8,      6,      8 } },  /* SDIO-REF */
 168         { CGU_SYS_IDIV_SPI_REF,  { 24,  24,     18,     24 } }, /* SPI-REF */
 169         { CGU_SYS_IDIV_I2C_REF,  { 4,   4,      3,      4 } },  /* I2C-REF */
 170         { CGU_SYS_IDIV_UART_REF, { 24,  24,     18,     24 } }, /* UART-REF */
 171         { CGU_SYS_IDIV_EBI_REF,  { 16,  16,     12,     16 } }, /* EBI-REF */
 172         { /* last one */ }
 173         }
 174 };
 175
 176 struct hsdk_pll_cfg {
 177         const u32 rate;
 178         const u8  idiv;
 179         const u8  fbdiv;
 180         const u8  odiv;
 181         const u8  band;
 182 };
 183
 184 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
 185         { 100000000,  0, 11, 3, 0 },
 186         { 125000000,  0, 14, 3, 0 },
 187         { 133000000,  0, 15, 3, 0 },
 188         { 150000000,  0, 17, 3, 0 },
 189         { 200000000,  1, 47, 3, 0 },
 190         { 233000000,  1, 27, 2, 0 },
 191         { 300000000,  1, 35, 2, 0 },
 192         { 333000000,  1, 39, 2, 0 },
 193         { 400000000,  1, 47, 2, 0 },
 194         { 500000000,  0, 14, 1, 0 },
 195         { 600000000,  0, 17, 1, 0 },
 196         { 700000000,  0, 20, 1, 0 },
 197         { 750000000,  1, 44, 1, 0 },
 198         { 800000000,  0, 23, 1, 0 },
 199         { 900000000,  1, 26, 0, 0 },
 200         { 1000000000, 1, 29, 0, 0 },
 201         { 1100000000, 1, 32, 0, 0 },
 202         { 1200000000, 1, 35, 0, 0 },
 203         { 1300000000, 1, 38, 0, 0 },
 204         { 1400000000, 1, 41, 0, 0 },
 205         { 1500000000, 1, 44, 0, 0 },
 206         { 1600000000, 1, 47, 0, 0 },
 207         {}
 208 };
 209
 210 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
 211         { 297000000,  0, 21, 2, 0 },
 212         { 540000000,  0, 19, 1, 0 },
 213         { 594000000,  0, 21, 1, 0 },
 214         {}
 215 };
 216
 217 struct hsdk_cgu_domain {
 218         /* PLLs registers */
 219         void __iomem *pll_regs;
 220         /* PLLs special registers */
 221         void __iomem *spec_regs;
 222         /* PLLs devdata */
 223         const struct hsdk_pll_devdata *pll;
 224
 225         /* Dividers registers */
 226         void __iomem *idiv_regs;
 227 };
 228
 229 struct hsdk_cgu_clk {
 230         /* CGU block register */
 231         void __iomem *cgu_regs;
 232         /* CREG block register */
 233         void __iomem *creg_regs;
 234
 235         /* The domain we are working with */
 236         struct hsdk_cgu_domain curr_domain;
 237 };
 238
 239 struct hsdk_pll_devdata {
 240         const u32 parent_rate;
 241         const struct hsdk_pll_cfg *const pll_cfg;
 242         const int (*const update_rate)(struct hsdk_cgu_clk *clk,
 243                                        unsigned long rate,
 244                                        const struct hsdk_pll_cfg *cfg);
 245 };
 246
 247 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
 248                                      const struct hsdk_pll_cfg *);
 249 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
 250                                      const struct hsdk_pll_cfg *);
 251
 252 static const struct hsdk_pll_devdata core_pll_dat = {
 253         .parent_rate = PARENT_RATE_33,
 254         .pll_cfg = asdt_pll_cfg,
 255         .update_rate = hsdk_pll_core_update_rate,
 256 };
 257
 258 static const struct hsdk_pll_devdata sdt_pll_dat = {
 259         .parent_rate = PARENT_RATE_33,
 260         .pll_cfg = asdt_pll_cfg,
 261         .update_rate = hsdk_pll_comm_update_rate,
 262 };
 263
 264 static const struct hsdk_pll_devdata hdmi_pll_dat = {
 265         .parent_rate = PARENT_RATE_27,
 266         .pll_cfg = hdmi_pll_cfg,
 267         .update_rate = hsdk_pll_comm_update_rate,
 268 };
 269
 270 static ulong idiv_set(struct clk *, ulong);
 271 static ulong cpu_clk_set(struct clk *, ulong);
 272 static ulong axi_clk_set(struct clk *, ulong);
 273 static ulong tun_clk_set(struct clk *, ulong);
 274 static ulong idiv_get(struct clk *);
 275 static int idiv_off(struct clk *);
 276 static ulong pll_set(struct clk *, ulong);
 277 static ulong pll_get(struct clk *);
 278
 279 struct cgu_clk_map {
 280         const u32 cgu_pll_oft;
 281         const u32 cgu_div_oft;
 282         const struct hsdk_pll_devdata *const pll_devdata;
 283         const ulong (*const get_rate)(struct clk *clk);
 284         const ulong (*const set_rate)(struct clk *clk, ulong rate);
 285         const int (*const disable)(struct clk *clk);
 286 };
 287
 288 static const struct cgu_clk_map clock_map[] = {
 289         { CGU_ARC_PLL, 0, &core_pll_dat, pll_get, pll_set, NULL },
 290         { CGU_ARC_PLL, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
 291         { CGU_DDR_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
 292         { CGU_SYS_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
 293         { CGU_SYS_PLL, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 294         { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
 295         { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 296         { CGU_SYS_PLL, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 297         { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 298         { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 299         { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 300         { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 301         { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 302         { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 303         { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 304         { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 305         { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 306         { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 307         { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 308         { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 309         { CGU_TUN_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
 310         { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
 311         { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 312         { CGU_TUN_PLL, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 313         { CGU_TUN_PLL, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
 314         { CGU_HDMI_PLL, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
 315         { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
 316 };
 317
 318 static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
 319 {
 320         iowrite32(val, clk->curr_domain.idiv_regs);
 321 }
 322
 323 static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
 324 {
 325         return ioread32(clk->curr_domain.idiv_regs);
 326 }
 327
 328 static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
 329 {
 330         iowrite32(val, clk->curr_domain.pll_regs + reg);
 331 }
 332
 333 static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
 334 {
 335         return ioread32(clk->curr_domain.pll_regs + reg);
 336 }
 337
 338 static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
 339 {
 340         iowrite32(val, clk->curr_domain.spec_regs + reg);
 341 }
 342
 343 static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
 344 {
 345         return ioread32(clk->curr_domain.spec_regs + reg);
 346 }
 347
 348 static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
 349                                     const struct hsdk_pll_cfg *cfg)
 350 {
 351         u32 val = 0;
 352
 353         /* Powerdown and Bypass bits should be cleared */
 354         val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
 355         val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
 356         val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
 357         val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
 358
 359         pr_debug("write configurarion: %#x\n", val);
 360
 361         hsdk_pll_write(clk, CGU_PLL_CTRL, val);
 362 }
 363
 364 static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
 365 {
 366         return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
 367 }
 368
 369 static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
 370 {
 371         return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
 372 }
 373
 374 static ulong pll_get(struct clk *sclk)
 375 {
 376         u32 val;
 377         u64 rate;
 378         u32 idiv, fbdiv, odiv;
 379         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 380         u32 parent_rate = clk->curr_domain.pll->parent_rate;
 381
 382         val = hsdk_pll_read(clk, CGU_PLL_CTRL);
 383
 384         pr_debug("current configurarion: %#x\n", val);
 385
 386         /* Check if PLL is bypassed */
 387         if (val & CGU_PLL_CTRL_BYPASS)
 388                 return parent_rate;
 389
 390         /* Check if PLL is disabled */
 391         if (val & CGU_PLL_CTRL_PD)
 392                 return 0;
 393
 394         /* input divider = reg.idiv + 1 */
 395         idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
 396         /* fb divider = 2*(reg.fbdiv + 1) */
 397         fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
 398         /* output divider = 2^(reg.odiv) */
 399         odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
 400
 401         rate = (u64)parent_rate * fbdiv;
 402         do_div(rate, idiv * odiv);
 403
 404         return rate;
 405 }
 406
 407 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
 408 {
 409         int i;
 410         unsigned long best_rate;
 411         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 412         const struct hsdk_pll_cfg *pll_cfg = clk->curr_domain.pll->pll_cfg;
 413
 414         if (pll_cfg[0].rate == 0)
 415                 return -EINVAL;
 416
 417         best_rate = pll_cfg[0].rate;
 418
 419         for (i = 1; pll_cfg[i].rate != 0; i++) {
 420                 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
 421                         best_rate = pll_cfg[i].rate;
 422         }
 423
 424         pr_debug("chosen best rate: %lu\n", best_rate);
 425
 426         return best_rate;
 427 }
 428
 429 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
 430                                      unsigned long rate,
 431                                      const struct hsdk_pll_cfg *cfg)
 432 {
 433         hsdk_pll_set_cfg(clk, cfg);
 434
 435         /*
 436          * Wait until CGU relocks and check error status.
 437          * If after timeout CGU is unlocked yet return error.
 438          */
 439         udelay(HSDK_PLL_MAX_LOCK_TIME);
 440         if (!hsdk_pll_is_locked(clk))
 441                 return -ETIMEDOUT;
 442
 443         if (hsdk_pll_is_err(clk))
 444                 return -EINVAL;
 445
 446         return 0;
 447 }
 448
 449 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
 450                                      unsigned long rate,
 451                                      const struct hsdk_pll_cfg *cfg)
 452 {
 453         /*
 454          * When core clock exceeds 500MHz, the divider for the interface
 455          * clock must be programmed to div-by-2.
 456          */
 457         if (rate > CORE_IF_CLK_THRESHOLD_HZ)
 458                 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
 459
 460         hsdk_pll_set_cfg(clk, cfg);
 461
 462         /*
 463          * Wait until CGU relocks and check error status.
 464          * If after timeout CGU is unlocked yet return error.
 465          */
 466         udelay(HSDK_PLL_MAX_LOCK_TIME);
 467         if (!hsdk_pll_is_locked(clk))
 468                 return -ETIMEDOUT;
 469
 470         if (hsdk_pll_is_err(clk))
 471                 return -EINVAL;
 472
 473         /*
 474          * Program divider to div-by-1 if we succesfuly set core clock below
 475          * 500MHz threshold.
 476          */
 477         if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
 478                 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
 479
 480         return 0;
 481 }
 482
 483 static ulong pll_set(struct clk *sclk, ulong rate)
 484 {
 485         int i;
 486         unsigned long best_rate;
 487         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 488         const struct hsdk_pll_devdata *pll = clk->curr_domain.pll;
 489         const struct hsdk_pll_cfg *pll_cfg = pll->pll_cfg;
 490
 491         best_rate = hsdk_pll_round_rate(sclk, rate);
 492
 493         for (i = 0; pll_cfg[i].rate != 0; i++)
 494                 if (pll_cfg[i].rate == best_rate)
 495                         return pll->update_rate(clk, best_rate, &pll_cfg[i]);
 496
 497         pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
 498                pll->parent_rate);
 499
 500         return -EINVAL;
 501 }
 502
 503 static int idiv_off(struct clk *sclk)
 504 {
 505         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 506
 507         hsdk_idiv_write(clk, 0);
 508
 509         return 0;
 510 }
 511
 512 static ulong idiv_get(struct clk *sclk)
 513 {
 514         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 515         ulong parent_rate = pll_get(sclk);
 516         u32 div_factor = hsdk_idiv_read(clk);
 517
 518         div_factor &= CGU_IDIV_MASK;
 519
 520         pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
 521
 522         if (div_factor == 0)
 523                 return 0;
 524
 525         return parent_rate / div_factor;
 526 }
 527
 528 /* Special behavior: wen we set this clock we set both idiv and pll */
 529 static ulong cpu_clk_set(struct clk *sclk, ulong rate)
 530 {
 531         ulong ret;
 532
 533         ret = pll_set(sclk, rate);
 534         idiv_set(sclk, rate);
 535
 536         return ret;
 537 }
 538
 539 /*
 540  * Special behavior:
 541  * when we set these clocks we set both PLL and all idiv dividers related to
 542  * this PLL domain.
 543  */
 544 static ulong common_div_clk_set(struct clk *sclk, ulong rate,
 545                                 const struct hsdk_div_full_cfg *cfg)
 546 {
 547         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 548         ulong pll_rate;
 549         int i, freq_idx = -1;
 550         ulong ret = 0;
 551
 552         pll_rate = pll_get(sclk);
 553
 554         for (i = 0; i < MAX_FREQ_VARIATIONS; i++) {
 555                 /* unused freq variations are filled with 0 */
 556                 if (!cfg->clk_rate[i])
 557                         break;
 558
 559                 if (cfg->clk_rate[i] == rate) {
 560                         freq_idx = i;
 561                         break;
 562                 }
 563         }
 564
 565         if (freq_idx < 0) {
 566                 pr_err("clk: invalid rate=%ld Hz\n", rate);
 567                 return -EINVAL;
 568         }
 569
 570         /* configure PLL before dividers */
 571         if (cfg->pll_rate[freq_idx] < pll_rate)
 572                 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
 573
 574         /* configure SYS dividers */
 575         for (i = 0; cfg->idiv[i].oft != 0; i++) {
 576                 clk->curr_domain.idiv_regs = clk->cgu_regs + cfg->idiv[i].oft;
 577                 hsdk_idiv_write(clk, cfg->idiv[i].val[freq_idx]);
 578         }
 579
 580         /* configure PLL after dividers */
 581         if (cfg->pll_rate[freq_idx] >= pll_rate)
 582                 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
 583
 584         return ret;
 585 }
 586
 587 static ulong axi_clk_set(struct clk *sclk, ulong rate)
 588 {
 589         return common_div_clk_set(sclk, rate, &axi_clk_cfg);
 590 }
 591
 592 static ulong tun_clk_set(struct clk *sclk, ulong rate)
 593 {
 594         return common_div_clk_set(sclk, rate, &tun_clk_cfg);
 595 }
 596
 597 static ulong idiv_set(struct clk *sclk, ulong rate)
 598 {
 599         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 600         ulong parent_rate = pll_get(sclk);
 601         u32 div_factor;
 602
 603         div_factor = parent_rate / rate;
 604         if (abs(rate - parent_rate / (div_factor + 1)) <=
 605             abs(rate - parent_rate / div_factor)) {
 606                 div_factor += 1;
 607         }
 608
 609         if (div_factor & ~CGU_IDIV_MASK) {
 610                 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
 611                        rate, parent_rate, div_factor, CGU_IDIV_MASK);
 612
 613                 div_factor = CGU_IDIV_MASK;
 614         }
 615
 616         if (div_factor == 0) {
 617                 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
 618                        rate, parent_rate, div_factor);
 619
 620                 div_factor = 1;
 621         }
 622
 623         hsdk_idiv_write(clk, div_factor);
 624
 625         return 0;
 626 }
 627
 628 static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
 629 {
 630         struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
 631
 632         if (sclk->id >= CGU_MAX_CLOCKS)
 633                 return -EINVAL;
 634
 635         clk->curr_domain.pll = clock_map[sclk->id].pll_devdata;
 636         clk->curr_domain.pll_regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
 637         clk->curr_domain.spec_regs = clk->creg_regs;
 638         clk->curr_domain.idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
 639
 640         return 0;
 641 }
 642
 643 static ulong hsdk_cgu_get_rate(struct clk *sclk)
 644 {
 645         if (hsdk_prepare_clock_tree_branch(sclk))
 646                 return -EINVAL;
 647
 648         return clock_map[sclk->id].get_rate(sclk);
 649 }
 650
 651 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
 652 {
 653         if (hsdk_prepare_clock_tree_branch(sclk))
 654                 return -EINVAL;
 655
 656         return clock_map[sclk->id].set_rate(sclk, rate);
 657 }
 658
 659 static int hsdk_cgu_disable(struct clk *sclk)
 660 {
 661         if (hsdk_prepare_clock_tree_branch(sclk))
 662                 return -EINVAL;
 663
 664         if (clock_map[sclk->id].disable)
 665                 return clock_map[sclk->id].disable(sclk);
 666
 667         return -ENOTSUPP;
 668 }
 669
 670 static const struct clk_ops hsdk_cgu_ops = {
 671         .set_rate = hsdk_cgu_set_rate,
 672         .get_rate = hsdk_cgu_get_rate,
 673         .disable = hsdk_cgu_disable,
 674 };
 675
 676 static int hsdk_cgu_clk_probe(struct udevice *dev)
 677 {
 678         struct hsdk_cgu_clk *hsdk_clk = dev_get_priv(dev);
 679
 680         BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
 681
 682         hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
 683         if (!hsdk_clk->cgu_regs)
 684                 return -EINVAL;
 685
 686         hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
 687         if (!hsdk_clk->creg_regs)
 688                 return -EINVAL;
 689
 690         return 0;
 691 }
 692
 693 static const struct udevice_id hsdk_cgu_clk_id[] = {
 694         { .compatible = "snps,hsdk-cgu-clock" },
 695         { }
 696 };
 697
 698 U_BOOT_DRIVER(hsdk_cgu_clk) = {
 699         .name = "hsdk-cgu-clk",
 700         .id = UCLASS_CLK,
 701         .of_match = hsdk_cgu_clk_id,
 702         .probe = hsdk_cgu_clk_probe,
 703         .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
 704         .ops = &hsdk_cgu_ops,
 705 };