1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Gated clock implementation
13 #include <clk-uclass.h>
14 #include <dm/device.h>
15 #include <linux/clk-provider.h>
19 #define UBOOT_DM_CLK_GATE "clk_gate"
22 * DOC: basic gatable clock which can gate and ungate it's output
24 * Traits of this clock:
25 * prepare - clk_(un)prepare only ensures parent is (un)prepared
26 * enable - clk_enable and clk_disable are functional & control gating
27 * rate - inherits rate from parent. No clk_set_rate support
28 * parent - fixed parent. No clk_set_parent support
32 * It works on following logic:
34 * For enabling clock, enable = 1
35 * set2dis = 1 -> clear bit -> set = 0
36 * set2dis = 0 -> set bit -> set = 1
38 * For disabling clock, enable = 0
39 * set2dis = 1 -> set bit -> set = 1
40 * set2dis = 0 -> clear bit -> set = 0
42 * So, result is always: enable xor set2dis.
44 static void clk_gate_endisable(struct clk *clk, int enable)
46 struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
47 dev_get_clk_ptr(clk->dev) : clk);
48 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
53 if (gate->flags & CLK_GATE_HIWORD_MASK) {
54 reg = BIT(gate->bit_idx + 16);
56 reg |= BIT(gate->bit_idx);
58 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
59 reg = gate->io_gate_val;
61 reg = readl(gate->reg);
65 reg |= BIT(gate->bit_idx);
67 reg &= ~BIT(gate->bit_idx);
70 writel(reg, gate->reg);
73 static int clk_gate_enable(struct clk *clk)
75 clk_gate_endisable(clk, 1);
80 static int clk_gate_disable(struct clk *clk)
82 clk_gate_endisable(clk, 0);
87 int clk_gate_is_enabled(struct clk *clk)
89 struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
90 dev_get_clk_ptr(clk->dev) : clk);
93 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
94 reg = gate->io_gate_val;
96 reg = readl(gate->reg);
99 /* if a set bit disables this clk, flip it before masking */
100 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
101 reg ^= BIT(gate->bit_idx);
103 reg &= BIT(gate->bit_idx);
108 const struct clk_ops clk_gate_ops = {
109 .enable = clk_gate_enable,
110 .disable = clk_gate_disable,
111 .get_rate = clk_generic_get_rate,
114 struct clk *clk_register_gate(struct device *dev, const char *name,
115 const char *parent_name, unsigned long flags,
116 void __iomem *reg, u8 bit_idx,
117 u8 clk_gate_flags, spinlock_t *lock)
119 struct clk_gate *gate;
123 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
125 pr_err("gate bit exceeds LOWORD field\n");
126 return ERR_PTR(-EINVAL);
130 /* allocate the gate */
131 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
133 return ERR_PTR(-ENOMEM);
135 /* struct clk_gate assignments */
137 gate->bit_idx = bit_idx;
138 gate->flags = clk_gate_flags;
139 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
140 gate->io_gate_val = *(u32 *)reg;
145 ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
154 U_BOOT_DRIVER(clk_gate) = {
155 .name = UBOOT_DM_CLK_GATE,
157 .ops = &clk_gate_ops,
158 .flags = DM_FLAG_PRE_RELOC,