drivers/clk/clk-divider.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
   8  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
   9  *
  10  */
  11
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <malloc.h>
  15 #include <clk-uclass.h>
  16 #include <dm/device.h>
  17 #include <dm/devres.h>
  18 #include <dm/uclass.h>
  19 #include <dm/lists.h>
  20 #include <dm/device-internal.h>
  21 #include <linux/bug.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/err.h>
  24 #include <linux/log2.h>
  25 #include <div64.h>
  26 #include <clk.h>
  27 #include "clk.h"
  28
  29 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
  30
  31 static unsigned int _get_table_div(const struct clk_div_table *table,
  32                                    unsigned int val)
  33 {
  34         const struct clk_div_table *clkt;
  35
  36         for (clkt = table; clkt->div; clkt++)
  37                 if (clkt->val == val)
  38                         return clkt->div;
  39         return 0;
  40 }
  41
  42 static unsigned int _get_div(const struct clk_div_table *table,
  43                              unsigned int val, unsigned long flags, u8 width)
  44 {
  45         if (flags & CLK_DIVIDER_ONE_BASED)
  46                 return val;
  47         if (flags & CLK_DIVIDER_POWER_OF_TWO)
  48                 return 1 << val;
  49         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  50                 return val ? val : clk_div_mask(width) + 1;
  51         if (table)
  52                 return _get_table_div(table, val);
  53         return val + 1;
  54 }
  55
  56 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
  57                                   unsigned int val,
  58                                   const struct clk_div_table *table,
  59                                   unsigned long flags, unsigned long width)
  60 {
  61         unsigned int div;
  62
  63         div = _get_div(table, val, flags, width);
  64         if (!div) {
  65                 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
  66                      "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  67                      clk_hw_get_name(hw));
  68                 return parent_rate;
  69         }
  70
  71         return DIV_ROUND_UP_ULL((u64)parent_rate, div);
  72 }
  73
  74 static ulong clk_divider_recalc_rate(struct clk *clk)
  75 {
  76         struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
  77                         dev_get_clk_ptr(clk->dev) : clk);
  78         unsigned long parent_rate = clk_get_parent_rate(clk);
  79         unsigned int val;
  80
  81 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  82         val = divider->io_divider_val;
  83 #else
  84         val = readl(divider->reg);
  85 #endif
  86         val >>= divider->shift;
  87         val &= clk_div_mask(divider->width);
  88
  89         return divider_recalc_rate(clk, parent_rate, val, divider->table,
  90                                    divider->flags, divider->width);
  91 }
  92
  93 static bool _is_valid_table_div(const struct clk_div_table *table,
  94                                 unsigned int div)
  95 {
  96         const struct clk_div_table *clkt;
  97
  98         for (clkt = table; clkt->div; clkt++)
  99                 if (clkt->div == div)
 100                         return true;
 101         return false;
 102 }
 103
 104 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
 105                           unsigned long flags)
 106 {
 107         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 108                 return is_power_of_2(div);
 109         if (table)
 110                 return _is_valid_table_div(table, div);
 111         return true;
 112 }
 113
 114 static unsigned int _get_table_val(const struct clk_div_table *table,
 115                                    unsigned int div)
 116 {
 117         const struct clk_div_table *clkt;
 118
 119         for (clkt = table; clkt->div; clkt++)
 120                 if (clkt->div == div)
 121                         return clkt->val;
 122         return 0;
 123 }
 124
 125 static unsigned int _get_val(const struct clk_div_table *table,
 126                              unsigned int div, unsigned long flags, u8 width)
 127 {
 128         if (flags & CLK_DIVIDER_ONE_BASED)
 129                 return div;
 130         if (flags & CLK_DIVIDER_POWER_OF_TWO)
 131                 return __ffs(div);
 132         if (flags & CLK_DIVIDER_MAX_AT_ZERO)
 133                 return (div == clk_div_mask(width) + 1) ? 0 : div;
 134         if (table)
 135                 return  _get_table_val(table, div);
 136         return div - 1;
 137 }
 138 int divider_get_val(unsigned long rate, unsigned long parent_rate,
 139                     const struct clk_div_table *table, u8 width,
 140                     unsigned long flags)
 141 {
 142         unsigned int div, value;
 143
 144         div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
 145
 146         if (!_is_valid_div(table, div, flags))
 147                 return -EINVAL;
 148
 149         value = _get_val(table, div, flags, width);
 150
 151         return min_t(unsigned int, value, clk_div_mask(width));
 152 }
 153
 154 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
 155 {
 156         struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
 157                         dev_get_clk_ptr(clk->dev) : clk);
 158         unsigned long parent_rate = clk_get_parent_rate(clk);
 159         int value;
 160         u32 val;
 161
 162         value = divider_get_val(rate, parent_rate, divider->table,
 163                                 divider->width, divider->flags);
 164         if (value < 0)
 165                 return value;
 166
 167         if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
 168                 val = clk_div_mask(divider->width) << (divider->shift + 16);
 169         } else {
 170                 val = readl(divider->reg);
 171                 val &= ~(clk_div_mask(divider->width) << divider->shift);
 172         }
 173         val |= (u32)value << divider->shift;
 174         writel(val, divider->reg);
 175
 176         return clk_get_rate(clk);
 177 }
 178
 179 const struct clk_ops clk_divider_ops = {
 180         .get_rate = clk_divider_recalc_rate,
 181         .set_rate = clk_divider_set_rate,
 182 };
 183
 184 static struct clk *_register_divider(struct device *dev, const char *name,
 185                 const char *parent_name, unsigned long flags,
 186                 void __iomem *reg, u8 shift, u8 width,
 187                 u8 clk_divider_flags, const struct clk_div_table *table)
 188 {
 189         struct clk_divider *div;
 190         struct clk *clk;
 191         int ret;
 192
 193         if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
 194                 if (width + shift > 16) {
 195                         pr_warn("divider value exceeds LOWORD field\n");
 196                         return ERR_PTR(-EINVAL);
 197                 }
 198         }
 199
 200         /* allocate the divider */
 201         div = kzalloc(sizeof(*div), GFP_KERNEL);
 202         if (!div)
 203                 return ERR_PTR(-ENOMEM);
 204
 205         /* struct clk_divider assignments */
 206         div->reg = reg;
 207         div->shift = shift;
 208         div->width = width;
 209         div->flags = clk_divider_flags;
 210         div->table = table;
 211 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
 212         div->io_divider_val = *(u32 *)reg;
 213 #endif
 214
 215         /* register the clock */
 216         clk = &div->clk;
 217
 218         ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
 219         if (ret) {
 220                 kfree(div);
 221                 return ERR_PTR(ret);
 222         }
 223
 224         return clk;
 225 }
 226
 227 struct clk *clk_register_divider(struct device *dev, const char *name,
 228                 const char *parent_name, unsigned long flags,
 229                 void __iomem *reg, u8 shift, u8 width,
 230                 u8 clk_divider_flags)
 231 {
 232         struct clk *clk;
 233
 234         clk =  _register_divider(dev, name, parent_name, flags, reg, shift,
 235                                  width, clk_divider_flags, NULL);
 236         if (IS_ERR(clk))
 237                 return ERR_CAST(clk);
 238         return clk;
 239 }
 240
 241 U_BOOT_DRIVER(ccf_clk_divider) = {
 242         .name   = UBOOT_DM_CLK_CCF_DIVIDER,
 243         .id     = UCLASS_CLK,
 244         .ops    = &clk_divider_ops,
 245         .flags = DM_FLAG_PRE_RELOC,
 246 };