1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
8 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
15 #include <clk-uclass.h>
16 #include <dm/device.h>
17 #include <dm/devres.h>
18 #include <dm/uclass.h>
20 #include <dm/device-internal.h>
21 #include <linux/clk-provider.h>
22 #include <linux/err.h>
23 #include <linux/log2.h>
28 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
30 static unsigned int _get_table_div(const struct clk_div_table *table,
33 const struct clk_div_table *clkt;
35 for (clkt = table; clkt->div; clkt++)
41 static unsigned int _get_div(const struct clk_div_table *table,
42 unsigned int val, unsigned long flags, u8 width)
44 if (flags & CLK_DIVIDER_ONE_BASED)
46 if (flags & CLK_DIVIDER_POWER_OF_TWO)
48 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
49 return val ? val : clk_div_mask(width) + 1;
51 return _get_table_div(table, val);
55 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
57 const struct clk_div_table *table,
58 unsigned long flags, unsigned long width)
62 div = _get_div(table, val, flags, width);
64 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
65 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
70 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
73 static ulong clk_divider_recalc_rate(struct clk *clk)
75 struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
76 dev_get_clk_ptr(clk->dev) : clk);
77 unsigned long parent_rate = clk_get_parent_rate(clk);
80 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
81 val = divider->io_divider_val;
83 val = readl(divider->reg);
85 val >>= divider->shift;
86 val &= clk_div_mask(divider->width);
88 return divider_recalc_rate(clk, parent_rate, val, divider->table,
89 divider->flags, divider->width);
92 static bool _is_valid_table_div(const struct clk_div_table *table,
95 const struct clk_div_table *clkt;
97 for (clkt = table; clkt->div; clkt++)
103 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
106 if (flags & CLK_DIVIDER_POWER_OF_TWO)
107 return is_power_of_2(div);
109 return _is_valid_table_div(table, div);
113 static unsigned int _get_table_val(const struct clk_div_table *table,
116 const struct clk_div_table *clkt;
118 for (clkt = table; clkt->div; clkt++)
119 if (clkt->div == div)
124 static unsigned int _get_val(const struct clk_div_table *table,
125 unsigned int div, unsigned long flags, u8 width)
127 if (flags & CLK_DIVIDER_ONE_BASED)
129 if (flags & CLK_DIVIDER_POWER_OF_TWO)
131 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
132 return (div == clk_div_mask(width) + 1) ? 0 : div;
134 return _get_table_val(table, div);
137 int divider_get_val(unsigned long rate, unsigned long parent_rate,
138 const struct clk_div_table *table, u8 width,
141 unsigned int div, value;
143 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
145 if (!_is_valid_div(table, div, flags))
148 value = _get_val(table, div, flags, width);
150 return min_t(unsigned int, value, clk_div_mask(width));
153 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
155 struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
156 dev_get_clk_ptr(clk->dev) : clk);
157 unsigned long parent_rate = clk_get_parent_rate(clk);
161 value = divider_get_val(rate, parent_rate, divider->table,
162 divider->width, divider->flags);
166 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
167 val = clk_div_mask(divider->width) << (divider->shift + 16);
169 val = readl(divider->reg);
170 val &= ~(clk_div_mask(divider->width) << divider->shift);
172 val |= (u32)value << divider->shift;
173 writel(val, divider->reg);
175 return clk_get_rate(clk);
178 const struct clk_ops clk_divider_ops = {
179 .get_rate = clk_divider_recalc_rate,
180 .set_rate = clk_divider_set_rate,
183 static struct clk *_register_divider(struct device *dev, const char *name,
184 const char *parent_name, unsigned long flags,
185 void __iomem *reg, u8 shift, u8 width,
186 u8 clk_divider_flags, const struct clk_div_table *table)
188 struct clk_divider *div;
192 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
193 if (width + shift > 16) {
194 pr_warn("divider value exceeds LOWORD field\n");
195 return ERR_PTR(-EINVAL);
199 /* allocate the divider */
200 div = kzalloc(sizeof(*div), GFP_KERNEL);
202 return ERR_PTR(-ENOMEM);
204 /* struct clk_divider assignments */
208 div->flags = clk_divider_flags;
210 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
211 div->io_divider_val = *(u32 *)reg;
214 /* register the clock */
217 ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
226 struct clk *clk_register_divider(struct device *dev, const char *name,
227 const char *parent_name, unsigned long flags,
228 void __iomem *reg, u8 shift, u8 width,
229 u8 clk_divider_flags)
233 clk = _register_divider(dev, name, parent_name, flags, reg, shift,
234 width, clk_divider_flags, NULL);
236 return ERR_CAST(clk);
240 U_BOOT_DRIVER(ccf_clk_divider) = {
241 .name = UBOOT_DM_CLK_CCF_DIVIDER,
243 .ops = &clk_divider_ops,
244 .flags = DM_FLAG_PRE_RELOC,