drivers/clk/at91/clk-system.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Atmel Corporation
   4  *               Wenyou.Yang <wenyou.yang@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <linux/bitops.h>
  11 #include <linux/io.h>
  12 #include <mach/at91_pmc.h>
  13 #include "pmc.h"
  14
  15 #define SYSTEM_MAX_ID           31
  16
  17 /**
  18  * at91_system_clk_bind() - for the system clock driver
  19  * Recursively bind its children as clk devices.
  20  *
  21  * @return: 0 on success, or negative error code on failure
  22  */
  23 static int at91_system_clk_bind(struct udevice *dev)
  24 {
  25         return at91_clk_sub_device_bind(dev, "system-clk");
  26 }
  27
  28 static const struct udevice_id at91_system_clk_match[] = {
  29         { .compatible = "atmel,at91rm9200-clk-system" },
  30         {}
  31 };
  32
  33 U_BOOT_DRIVER(at91_system_clk) = {
  34         .name = "at91-system-clk",
  35         .id = UCLASS_MISC,
  36         .of_match = at91_system_clk_match,
  37         .bind = at91_system_clk_bind,
  38 };
  39
  40 /*----------------------------------------------------------*/
  41
  42 static inline int is_pck(int id)
  43 {
  44         return (id >= 8) && (id <= 15);
  45 }
  46
  47 static ulong system_clk_get_rate(struct clk *clk)
  48 {
  49         struct clk clk_dev;
  50         int ret;
  51
  52         ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  53         if (ret)
  54                 return -EINVAL;
  55
  56         return clk_get_rate(&clk_dev);
  57 }
  58
  59 static ulong system_clk_set_rate(struct clk *clk, ulong rate)
  60 {
  61         struct clk clk_dev;
  62         int ret;
  63
  64         ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  65         if (ret)
  66                 return -EINVAL;
  67
  68         return clk_set_rate(&clk_dev, rate);
  69 }
  70
  71 static int system_clk_enable(struct clk *clk)
  72 {
  73         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  74         struct at91_pmc *pmc = plat->reg_base;
  75         u32 mask;
  76
  77         if (clk->id > SYSTEM_MAX_ID)
  78                 return -EINVAL;
  79
  80         mask = BIT(clk->id);
  81
  82         writel(mask, &pmc->scer);
  83
  84         /**
  85          * For the programmable clocks the Ready status in the PMC
  86          * status register should be checked after enabling.
  87          * For other clocks this is unnecessary.
  88          */
  89         if (!is_pck(clk->id))
  90                 return 0;
  91
  92         while (!(readl(&pmc->sr) & mask))
  93                 ;
  94
  95         return 0;
  96 }
  97
  98 static struct clk_ops system_clk_ops = {
  99         .of_xlate = at91_clk_of_xlate,
 100         .get_rate = system_clk_get_rate,
 101         .set_rate = system_clk_set_rate,
 102         .enable = system_clk_enable,
 103 };
 104
 105 U_BOOT_DRIVER(system_clk) = {
 106         .name = "system-clk",
 107         .id = UCLASS_CLK,
 108         .probe = at91_clk_probe,
 109         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 110         .ops = &system_clk_ops,
 111 };