2 * Copyright (C) 2016 Atmel Corporation
3 * Wenyou.Yang <wenyou.yang@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
10 #include <dm/device.h>
12 #include <mach/at91_pmc.h>
15 #define PERIPHERAL_ID_MIN 2
16 #define PERIPHERAL_ID_MAX 31
17 #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
20 * sam9x5_periph_clk_bind() - for the periph clock driver
21 * Recursively bind its children as clk devices.
23 * @return: 0 on success, or negative error code on failure
25 static int sam9x5_periph_clk_bind(struct udevice *dev)
27 return at91_clk_sub_device_bind(dev, "periph-clk");
30 static const struct udevice_id sam9x5_periph_clk_match[] = {
31 { .compatible = "atmel,at91sam9x5-clk-peripheral" },
35 U_BOOT_DRIVER(sam9x5_periph_clk) = {
36 .name = "sam9x5-periph-clk",
38 .of_match = sam9x5_periph_clk_match,
39 .bind = sam9x5_periph_clk_bind,
42 /*---------------------------------------------------------*/
44 static int periph_clk_enable(struct clk *clk)
46 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
47 struct at91_pmc *pmc = plat->reg_base;
49 if (clk->id < PERIPHERAL_ID_MIN)
52 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
53 setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
58 static ulong periph_get_rate(struct clk *clk)
65 dev = dev_get_parent(clk->dev);
67 ret = clk_get_by_index(dev, 0, &clk_dev);
71 clk_rate = clk_get_rate(&clk_dev);
78 static struct clk_ops periph_clk_ops = {
79 .of_xlate = at91_clk_of_xlate,
80 .enable = periph_clk_enable,
81 .get_rate = periph_get_rate,
84 U_BOOT_DRIVER(clk_periph) = {
87 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
88 .probe = at91_clk_probe,
89 .ops = &periph_clk_ops,