1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 #include <linux/clk-provider.h>
7 #include <linux/clkdev.h>
8 #include <linux/clk/at91_pmc.h>
9 #include <linux/delay.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/regmap.h>
15 #define SLOW_CLOCK_FREQ 32768
17 #define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
19 #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
20 #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
22 #define MOR_KEY_MASK (0xff << 16)
24 #define clk_main_parent_select(s) (((s) & \
26 AT91_PMC_OSCBYPASS)) ? 1 : 0)
30 struct regmap *regmap;
33 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
35 struct clk_main_rc_osc {
37 struct regmap *regmap;
38 unsigned long frequency;
39 unsigned long accuracy;
42 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
44 struct clk_rm9200_main {
46 struct regmap *regmap;
49 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
51 struct clk_sam9x5_main {
53 struct regmap *regmap;
57 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
59 static inline bool clk_main_osc_ready(struct regmap *regmap)
63 regmap_read(regmap, AT91_PMC_SR, &status);
65 return status & AT91_PMC_MOSCS;
68 static int clk_main_osc_prepare(struct clk_hw *hw)
70 struct clk_main_osc *osc = to_clk_main_osc(hw);
71 struct regmap *regmap = osc->regmap;
74 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
77 if (tmp & AT91_PMC_OSCBYPASS)
80 if (!(tmp & AT91_PMC_MOSCEN)) {
81 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
82 regmap_write(regmap, AT91_CKGR_MOR, tmp);
85 while (!clk_main_osc_ready(regmap))
91 static void clk_main_osc_unprepare(struct clk_hw *hw)
93 struct clk_main_osc *osc = to_clk_main_osc(hw);
94 struct regmap *regmap = osc->regmap;
97 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
98 if (tmp & AT91_PMC_OSCBYPASS)
101 if (!(tmp & AT91_PMC_MOSCEN))
104 tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
105 regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
108 static int clk_main_osc_is_prepared(struct clk_hw *hw)
110 struct clk_main_osc *osc = to_clk_main_osc(hw);
111 struct regmap *regmap = osc->regmap;
114 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
115 if (tmp & AT91_PMC_OSCBYPASS)
118 regmap_read(regmap, AT91_PMC_SR, &status);
120 return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
123 static const struct clk_ops main_osc_ops = {
124 .prepare = clk_main_osc_prepare,
125 .unprepare = clk_main_osc_unprepare,
126 .is_prepared = clk_main_osc_is_prepared,
129 struct clk_hw * __init
130 at91_clk_register_main_osc(struct regmap *regmap,
132 const char *parent_name,
135 struct clk_main_osc *osc;
136 struct clk_init_data init;
140 if (!name || !parent_name)
141 return ERR_PTR(-EINVAL);
143 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
145 return ERR_PTR(-ENOMEM);
148 init.ops = &main_osc_ops;
149 init.parent_names = &parent_name;
150 init.num_parents = 1;
151 init.flags = CLK_IGNORE_UNUSED;
153 osc->hw.init = &init;
154 osc->regmap = regmap;
157 regmap_update_bits(regmap,
158 AT91_CKGR_MOR, MOR_KEY_MASK |
160 AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
163 ret = clk_hw_register(NULL, &osc->hw);
172 static bool clk_main_rc_osc_ready(struct regmap *regmap)
176 regmap_read(regmap, AT91_PMC_SR, &status);
178 return status & AT91_PMC_MOSCRCS;
181 static int clk_main_rc_osc_prepare(struct clk_hw *hw)
183 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
184 struct regmap *regmap = osc->regmap;
187 regmap_read(regmap, AT91_CKGR_MOR, &mor);
189 if (!(mor & AT91_PMC_MOSCRCEN))
190 regmap_update_bits(regmap, AT91_CKGR_MOR,
191 MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
192 AT91_PMC_MOSCRCEN | AT91_PMC_KEY);
194 while (!clk_main_rc_osc_ready(regmap))
200 static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
202 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
203 struct regmap *regmap = osc->regmap;
206 regmap_read(regmap, AT91_CKGR_MOR, &mor);
208 if (!(mor & AT91_PMC_MOSCRCEN))
211 regmap_update_bits(regmap, AT91_CKGR_MOR,
212 MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY);
215 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
217 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
218 struct regmap *regmap = osc->regmap;
219 unsigned int mor, status;
221 regmap_read(regmap, AT91_CKGR_MOR, &mor);
222 regmap_read(regmap, AT91_PMC_SR, &status);
224 return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS);
227 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
228 unsigned long parent_rate)
230 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
232 return osc->frequency;
235 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
236 unsigned long parent_acc)
238 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
240 return osc->accuracy;
243 static const struct clk_ops main_rc_osc_ops = {
244 .prepare = clk_main_rc_osc_prepare,
245 .unprepare = clk_main_rc_osc_unprepare,
246 .is_prepared = clk_main_rc_osc_is_prepared,
247 .recalc_rate = clk_main_rc_osc_recalc_rate,
248 .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
251 struct clk_hw * __init
252 at91_clk_register_main_rc_osc(struct regmap *regmap,
254 u32 frequency, u32 accuracy)
256 struct clk_main_rc_osc *osc;
257 struct clk_init_data init;
261 if (!name || !frequency)
262 return ERR_PTR(-EINVAL);
264 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
266 return ERR_PTR(-ENOMEM);
269 init.ops = &main_rc_osc_ops;
270 init.parent_names = NULL;
271 init.num_parents = 0;
272 init.flags = CLK_IGNORE_UNUSED;
274 osc->hw.init = &init;
275 osc->regmap = regmap;
276 osc->frequency = frequency;
277 osc->accuracy = accuracy;
280 ret = clk_hw_register(NULL, hw);
289 static int clk_main_probe_frequency(struct regmap *regmap)
291 unsigned long prep_time, timeout;
294 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
297 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
298 if (mcfr & AT91_PMC_MAINRDY)
300 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
301 } while (time_before(prep_time, timeout));
306 static unsigned long clk_main_recalc_rate(struct regmap *regmap,
307 unsigned long parent_rate)
314 pr_warn("Main crystal frequency not set, using approximate value\n");
315 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
316 if (!(mcfr & AT91_PMC_MAINRDY))
319 return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
322 static int clk_rm9200_main_prepare(struct clk_hw *hw)
324 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
326 return clk_main_probe_frequency(clkmain->regmap);
329 static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
331 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
334 regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status);
336 return status & AT91_PMC_MAINRDY ? 1 : 0;
339 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
340 unsigned long parent_rate)
342 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
344 return clk_main_recalc_rate(clkmain->regmap, parent_rate);
347 static const struct clk_ops rm9200_main_ops = {
348 .prepare = clk_rm9200_main_prepare,
349 .is_prepared = clk_rm9200_main_is_prepared,
350 .recalc_rate = clk_rm9200_main_recalc_rate,
353 struct clk_hw * __init
354 at91_clk_register_rm9200_main(struct regmap *regmap,
356 const char *parent_name)
358 struct clk_rm9200_main *clkmain;
359 struct clk_init_data init;
364 return ERR_PTR(-EINVAL);
367 return ERR_PTR(-EINVAL);
369 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
371 return ERR_PTR(-ENOMEM);
374 init.ops = &rm9200_main_ops;
375 init.parent_names = &parent_name;
376 init.num_parents = 1;
379 clkmain->hw.init = &init;
380 clkmain->regmap = regmap;
383 ret = clk_hw_register(NULL, &clkmain->hw);
392 static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
396 regmap_read(regmap, AT91_PMC_SR, &status);
398 return status & AT91_PMC_MOSCSELS ? 1 : 0;
401 static int clk_sam9x5_main_prepare(struct clk_hw *hw)
403 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
404 struct regmap *regmap = clkmain->regmap;
406 while (!clk_sam9x5_main_ready(regmap))
409 return clk_main_probe_frequency(regmap);
412 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
414 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
416 return clk_sam9x5_main_ready(clkmain->regmap);
419 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
420 unsigned long parent_rate)
422 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
424 return clk_main_recalc_rate(clkmain->regmap, parent_rate);
427 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
429 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
430 struct regmap *regmap = clkmain->regmap;
436 regmap_read(regmap, AT91_CKGR_MOR, &tmp);
437 tmp &= ~MOR_KEY_MASK;
439 if (index && !(tmp & AT91_PMC_MOSCSEL))
440 regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
441 else if (!index && (tmp & AT91_PMC_MOSCSEL))
442 regmap_write(regmap, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
444 while (!clk_sam9x5_main_ready(regmap))
450 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
452 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
455 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
457 return clk_main_parent_select(status);
460 static const struct clk_ops sam9x5_main_ops = {
461 .prepare = clk_sam9x5_main_prepare,
462 .is_prepared = clk_sam9x5_main_is_prepared,
463 .recalc_rate = clk_sam9x5_main_recalc_rate,
464 .set_parent = clk_sam9x5_main_set_parent,
465 .get_parent = clk_sam9x5_main_get_parent,
468 struct clk_hw * __init
469 at91_clk_register_sam9x5_main(struct regmap *regmap,
471 const char **parent_names,
474 struct clk_sam9x5_main *clkmain;
475 struct clk_init_data init;
481 return ERR_PTR(-EINVAL);
483 if (!parent_names || !num_parents)
484 return ERR_PTR(-EINVAL);
486 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
488 return ERR_PTR(-ENOMEM);
491 init.ops = &sam9x5_main_ops;
492 init.parent_names = parent_names;
493 init.num_parents = num_parents;
494 init.flags = CLK_SET_PARENT_GATE;
496 clkmain->hw.init = &init;
497 clkmain->regmap = regmap;
498 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
499 clkmain->parent = clk_main_parent_select(status);
502 ret = clk_hw_register(NULL, &clkmain->hw);