1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
8 #include <clk-uclass.h>
12 #include <mach/at91_pmc.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define H32MX_MAX_FREQ 90000000
19 static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
21 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
22 struct at91_pmc *pmc = plat->reg_base;
23 ulong rate = gd->arch.mck_rate_hz;
25 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
28 if (rate > H32MX_MAX_FREQ)
29 dev_dbg(clk->dev, "H32MX clock is too fast\n");
34 static struct clk_ops sama5d4_h32mx_clk_ops = {
35 .get_rate = sama5d4_h32mx_clk_get_rate,
38 static int sama5d4_h32mx_clk_probe(struct udevice *dev)
40 return at91_pmc_core_probe(dev);
43 static const struct udevice_id sama5d4_h32mx_clk_match[] = {
44 { .compatible = "atmel,sama5d4-clk-h32mx" },
48 U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
49 .name = "sama5d4-h32mx-clk",
51 .of_match = sama5d4_h32mx_clk_match,
52 .probe = sama5d4_h32mx_clk_probe,
53 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
54 .ops = &sama5d4_h32mx_clk_ops,