1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
8 #include <clk-uclass.h>
12 #include <linux/err.h>
14 #include <mach/at91_pmc.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #define GENERATED_SOURCE_MAX 6
20 #define GENERATED_MAX_DIV 255
23 * generated_clk_bind() - for the generated clock driver
24 * Recursively bind its children as clk devices.
26 * @return: 0 on success, or negative error code on failure
28 static int generated_clk_bind(struct udevice *dev)
30 return at91_clk_sub_device_bind(dev, "generic-clk");
33 static const struct udevice_id generated_clk_match[] = {
34 { .compatible = "atmel,sama5d2-clk-generated" },
38 U_BOOT_DRIVER(generated_clk) = {
39 .name = "generated-clk",
41 .of_match = generated_clk_match,
42 .bind = generated_clk_bind,
45 /*-------------------------------------------------------------*/
47 struct generic_clk_priv {
51 static ulong generic_clk_get_rate(struct clk *clk)
53 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
54 struct at91_pmc *pmc = plat->reg_base;
58 u8 clock_source, parent_index;
61 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
62 tmp = readl(&pmc->pcr);
63 clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
64 AT91_PMC_PCR_GCKCSS_MASK;
65 gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
67 parent_index = clock_source - 1;
68 ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
72 clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
79 static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
81 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
82 struct at91_pmc *pmc = plat->reg_base;
83 struct generic_clk_priv *priv = dev_get_priv(clk->dev);
84 struct clk parent, best_parent;
85 ulong tmp_rate, best_rate = rate, parent_rate;
86 int tmp_diff, best_diff = -1;
87 u32 div, best_div = 0;
88 u8 best_parent_index, best_clock_source = 0;
93 for (i = 0; i < priv->num_parents; i++) {
94 ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
98 parent_rate = clk_get_rate(&parent);
99 if (IS_ERR_VALUE(parent_rate))
102 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
103 tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
104 tmp_diff = abs(rate - tmp_rate);
106 if (best_diff < 0 || best_diff > tmp_diff) {
107 best_rate = tmp_rate;
108 best_diff = tmp_diff;
111 best_parent = parent;
112 best_parent_index = i;
113 best_clock_source = best_parent_index + 1;
116 if (!best_diff || tmp_rate < rate)
124 debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
125 best_parent.dev->name, best_rate, best_div);
127 ret = clk_enable(&best_parent);
131 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
132 tmp = readl(&pmc->pcr);
133 tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
134 tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
135 AT91_PMC_PCR_CMD_WRITE |
136 AT91_PMC_PCR_GCKDIV_(best_div) |
138 writel(tmp, &pmc->pcr);
140 while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
146 static struct clk_ops generic_clk_ops = {
147 .of_xlate = at91_clk_of_xlate,
148 .get_rate = generic_clk_get_rate,
149 .set_rate = generic_clk_set_rate,
152 static int generic_clk_ofdata_to_platdata(struct udevice *dev)
154 struct generic_clk_priv *priv = dev_get_priv(dev);
155 u32 cells[GENERATED_SOURCE_MAX];
158 num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
159 dev_of_offset(dev_get_parent(dev)), "clocks", cells,
160 GENERATED_SOURCE_MAX);
165 priv->num_parents = num_parents;
170 U_BOOT_DRIVER(generic_clk) = {
171 .name = "generic-clk",
173 .probe = at91_clk_probe,
174 .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
175 .priv_auto_alloc_size = sizeof(struct generic_clk_priv),
176 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
177 .ops = &generic_clk_ops,