drivers/clk/altera/clk-agilex.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2019 Intel Corporation <www.intel.com>
   4  */
   5
   6 #ifndef _CLK_AGILEX_
   7 #define _CLK_AGILEX_
   8
   9 #ifndef __ASSEMBLY__
  10 #include <linux/bitops.h>
  11 #endif
  12
  13 #define CM_REG_READL(plat, reg)                         \
  14         readl((plat)->regs + (reg))
  15
  16 #define CM_REG_WRITEL(plat, data, reg)                  \
  17         writel(data, (plat)->regs + (reg))
  18
  19 #define CM_REG_CLRBITS(plat, reg, clear)                \
  20         clrbits_le32((plat)->regs + (reg), (clear))
  21
  22 #define CM_REG_SETBITS(plat, reg, set)                  \
  23         setbits_le32((plat)->regs + (reg), (set))
  24
  25 struct cm_config {
  26         /* main group */
  27         u32 main_pll_mpuclk;
  28         u32 main_pll_nocclk;
  29         u32 main_pll_nocdiv;
  30         u32 main_pll_pllglob;
  31         u32 main_pll_fdbck;
  32         u32 main_pll_pllc0;
  33         u32 main_pll_pllc1;
  34         u32 main_pll_pllc2;
  35         u32 main_pll_pllc3;
  36         u32 main_pll_pllm;
  37
  38         /* peripheral group */
  39         u32 per_pll_emacctl;
  40         u32 per_pll_gpiodiv;
  41         u32 per_pll_pllglob;
  42         u32 per_pll_fdbck;
  43         u32 per_pll_pllc0;
  44         u32 per_pll_pllc1;
  45         u32 per_pll_pllc2;
  46         u32 per_pll_pllc3;
  47         u32 per_pll_pllm;
  48
  49         /* altera group */
  50         u32 alt_emacactr;
  51         u32 alt_emacbctr;
  52         u32 alt_emacptpctr;
  53         u32 alt_gpiodbctr;
  54         u32 alt_sdmmcctr;
  55         u32 alt_s2fuser0ctr;
  56         u32 alt_s2fuser1ctr;
  57         u32 alt_psirefctr;
  58
  59         /* incoming clock */
  60         u32 hps_osc_clk_hz;
  61         u32 fpga_clk_hz;
  62         u32 spare[3];
  63 };
  64
  65 /* Clock Manager registers */
  66 #define CLKMGR_CTRL                             0
  67 #define CLKMGR_STAT                             4
  68 #define CLKMGR_TESTIOCTRL                       8
  69 #define CLKMGR_INTRGEN                          0x0c
  70 #define CLKMGR_INTRMSK                          0x10
  71 #define CLKMGR_INTRCLR                          0x14
  72 #define CLKMGR_INTRSTS                          0x18
  73 #define CLKMGR_INTRSTK                          0x1c
  74 #define CLKMGR_INTRRAW                          0x20
  75
  76 /* Clock Manager Main PPL group registers */
  77 #define CLKMGR_MAINPLL_EN                       0x24
  78 #define CLKMGR_MAINPLL_ENS                      0x28
  79 #define CLKMGR_MAINPLL_ENR                      0x2c
  80 #define CLKMGR_MAINPLL_BYPASS                   0x30
  81 #define CLKMGR_MAINPLL_BYPASSS                  0x34
  82 #define CLKMGR_MAINPLL_BYPASSR                  0x38
  83 #define CLKMGR_MAINPLL_MPUCLK                   0x3c
  84 #define CLKMGR_MAINPLL_NOCCLK                   0x40
  85 #define CLKMGR_MAINPLL_NOCDIV                   0x44
  86 #define CLKMGR_MAINPLL_PLLGLOB                  0x48
  87 #define CLKMGR_MAINPLL_FDBCK                    0x4c
  88 #define CLKMGR_MAINPLL_MEM                      0x50
  89 #define CLKMGR_MAINPLL_MEMSTAT                  0x54
  90 #define CLKMGR_MAINPLL_PLLC0                    0x58
  91 #define CLKMGR_MAINPLL_PLLC1                    0x5c
  92 #define CLKMGR_MAINPLL_VCOCALIB                 0x60
  93 #define CLKMGR_MAINPLL_PLLC2                    0x64
  94 #define CLKMGR_MAINPLL_PLLC3                    0x68
  95 #define CLKMGR_MAINPLL_PLLM                     0x6c
  96 #define CLKMGR_MAINPLL_FHOP                     0x70
  97 #define CLKMGR_MAINPLL_SSC                      0x74
  98 #define CLKMGR_MAINPLL_LOSTLOCK                 0x78
  99
 100 /* Clock Manager Peripheral PPL group registers */
 101 #define CLKMGR_PERPLL_EN                        0x7c
 102 #define CLKMGR_PERPLL_ENS                       0x80
 103 #define CLKMGR_PERPLL_ENR                       0x84
 104 #define CLKMGR_PERPLL_BYPASS                    0x88
 105 #define CLKMGR_PERPLL_BYPASSS                   0x8c
 106 #define CLKMGR_PERPLL_BYPASSR                   0x90
 107 #define CLKMGR_PERPLL_EMACCTL                   0x94
 108 #define CLKMGR_PERPLL_GPIODIV                   0x98
 109 #define CLKMGR_PERPLL_PLLGLOB                   0x9c
 110 #define CLKMGR_PERPLL_FDBCK                     0xa0
 111 #define CLKMGR_PERPLL_MEM                       0xa4
 112 #define CLKMGR_PERPLL_MEMSTAT                   0xa8
 113 #define CLKMGR_PERPLL_PLLC0                     0xac
 114 #define CLKMGR_PERPLL_PLLC1                     0xb0
 115 #define CLKMGR_PERPLL_VCOCALIB                  0xb4
 116 #define CLKMGR_PERPLL_PLLC2                     0xb8
 117 #define CLKMGR_PERPLL_PLLC3                     0xbc
 118 #define CLKMGR_PERPLL_PLLM                      0xc0
 119 #define CLKMGR_PERPLL_FHOP                      0xc4
 120 #define CLKMGR_PERPLL_SSC                       0xc8
 121 #define CLKMGR_PERPLL_LOSTLOCK                  0xcc
 122
 123 /* Clock Manager Altera group registers */
 124 #define CLKMGR_ALTR_JTAG                        0xd0
 125 #define CLKMGR_ALTR_EMACACTR                    0xd4
 126 #define CLKMGR_ALTR_EMACBCTR                    0xd8
 127 #define CLKMGR_ALTR_EMACPTPCTR                  0xdc
 128 #define CLKMGR_ALTR_GPIODBCTR                   0xe0
 129 #define CLKMGR_ALTR_SDMMCCTR                    0xe4
 130 #define CLKMGR_ALTR_S2FUSER0CTR                 0xe8
 131 #define CLKMGR_ALTR_S2FUSER1CTR                 0xec
 132 #define CLKMGR_ALTR_PSIREFCTR                   0xf0
 133 #define CLKMGR_ALTR_EXTCNTRST                   0xf4
 134
 135 #define CLKMGR_CTRL_BOOTMODE                    BIT(0)
 136
 137 #define CLKMGR_STAT_BUSY                        BIT(0)
 138 #define CLKMGR_STAT_MAINPLL_LOCKED              BIT(8)
 139 #define CLKMGR_STAT_MAIN_TRANS                  BIT(9)
 140 #define CLKMGR_STAT_PERPLL_LOCKED               BIT(16)
 141 #define CLKMGR_STAT_PERF_TRANS                  BIT(17)
 142 #define CLKMGR_STAT_BOOTMODE                    BIT(24)
 143 #define CLKMGR_STAT_BOOTCLKSRC                  BIT(25)
 144
 145 #define CLKMGR_STAT_ALLPLL_LOCKED_MASK          \
 146         (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
 147
 148 #define CLKMGR_INTER_MAINPLLLOCKED_MASK         0x00000001
 149 #define CLKMGR_INTER_PERPLLLOCKED_MASK          0x00000002
 150 #define CLKMGR_INTER_MAINPLLLOST_MASK           0x00000004
 151 #define CLKMGR_INTER_PERPLLLOST_MASK            0x00000008
 152
 153 #define CLKMGR_CLKSRC_MASK                      GENMASK(18, 16)
 154 #define CLKMGR_CLKSRC_OFFSET                    16
 155 #define CLKMGR_CLKSRC_MAIN                      0
 156 #define CLKMGR_CLKSRC_PER                       1
 157 #define CLKMGR_CLKSRC_OSC1                      2
 158 #define CLKMGR_CLKSRC_INTOSC                    3
 159 #define CLKMGR_CLKSRC_FPGA                      4
 160 #define CLKMGR_CLKCNT_MSK                       GENMASK(10, 0)
 161
 162 #define CLKMGR_BYPASS_MAINPLL_ALL               0x7
 163 #define CLKMGR_BYPASS_PERPLL_ALL                0x7f
 164
 165 #define CLKMGR_NOCDIV_L4MAIN_OFFSET             0
 166 #define CLKMGR_NOCDIV_L4MPCLK_OFFSET            8
 167 #define CLKMGR_NOCDIV_L4SPCLK_OFFSET            16
 168 #define CLKMGR_NOCDIV_CSATCLK_OFFSET            24
 169 #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET         26
 170 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET          28
 171 #define CLKMGR_NOCDIV_DIVIDER_MASK              0x3
 172
 173 #define CLKMGR_PLLGLOB_PD_MASK                          BIT(0)
 174 #define CLKMGR_PLLGLOB_RST_MASK                         BIT(1)
 175 #define CLKMGR_PLLGLOB_AREFCLKDIV_MASK                  GENMASK(11, 8)
 176 #define CLKMGR_PLLGLOB_DREFCLKDIV_MASK                  GENMASK(13, 12)
 177 #define CLKMGR_PLLGLOB_REFCLKDIV_MASK                   GENMASK(13, 8)
 178 #define CLKMGR_PLLGLOB_MODCLKDIV_MASK                   GENMASK(24, 27)
 179 #define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET                8
 180 #define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET                12
 181 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET                 8
 182 #define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET                 24
 183 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK                    GENMASK(17, 16)
 184 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET                  16
 185 #define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK         BIT(29)
 186
 187 #define CLKMGR_VCO_PSRC_EOSC1                   0
 188 #define CLKMGR_VCO_PSRC_INTOSC                  1
 189 #define CLKMGR_VCO_PSRC_F2S                     2
 190
 191 #define CLKMGR_MEM_REQ_SET_MSK                  BIT(24)
 192 #define CLKMGR_MEM_WR_SET_MSK                   BIT(25)
 193 #define CLKMGR_MEM_ERR_MSK                      BIT(26)
 194 #define CLKMGR_MEM_WDAT_LSB_OFFSET              16
 195 #define CLKMGR_MEM_ADDR_MASK                    GENMASK(15, 0)
 196 #define CLKMGR_MEM_ADDR_START                   0x00004000
 197
 198 #define CLKMGR_PLLCX_EN_SET_MSK                 BIT(27)
 199 #define CLKMGR_PLLCX_MUTE_SET_MSK               BIT(28)
 200
 201 #define CLKMGR_VCOCALIB_MSCNT_MASK              GENMASK(23, 16)
 202 #define CLKMGR_VCOCALIB_MSCNT_OFFSET            16
 203 #define CLKMGR_VCOCALIB_HSCNT_MASK              GENMASK(9, 0)
 204 #define CLKMGR_VCOCALIB_MSCNT_CONST             100
 205 #define CLKMGR_VCOCALIB_HSCNT_CONST             4
 206
 207 #define CLKMGR_PLLM_MDIV_MASK                   GENMASK(9, 0)
 208
 209 #define CLKMGR_LOSTLOCK_SET_MASK                BIT(0)
 210
 211 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK               BIT(5)
 212 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET       26
 213 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK         BIT(26)
 214 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET       27
 215 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK         BIT(27)
 216 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET       28
 217 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK         BIT(28)
 218
 219 #define CLKMGR_ALT_EMACCTR_SRC_OFFSET           16
 220 #define CLKMGR_ALT_EMACCTR_SRC_MASK             GENMASK(18, 16)
 221 #define CLKMGR_ALT_EMACCTR_CNT_OFFSET           0
 222 #define CLKMGR_ALT_EMACCTR_CNT_MASK             GENMASK(10, 0)
 223
 224 #define CLKMGR_ALT_EXTCNTRST_EMACACNTRST        BIT(0)
 225 #define CLKMGR_ALT_EXTCNTRST_EMACBCNTRST        BIT(1)
 226 #define CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST      BIT(2)
 227 #define CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST       BIT(3)
 228 #define CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST        BIT(4)
 229 #define CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST     BIT(5)
 230 #define CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST     BIT(6)
 231 #define CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST       BIT(7)
 232 #define CLKMGR_ALT_EXTCNTRST_ALLCNTRST          \
 233         (CLKMGR_ALT_EXTCNTRST_EMACACNTRST |     \
 234          CLKMGR_ALT_EXTCNTRST_EMACBCNTRST |     \
 235          CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST |   \
 236          CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST |    \
 237          CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST |     \
 238          CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST |  \
 239          CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST |  \
 240          CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST)
 241 #endif /* _CLK_AGILEX_ */