drivers/clk/actions/owl-s500.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Actions Semi Owl S500 SoC clock driver
   4  *
   5  * Copyright (c) 2014 Actions Semi Inc.
   6  * Author: David Liu <liuwei@actions-semi.com>
   7  *
   8  * Copyright (c) 2018 Linaro Ltd.
   9  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10  *
  11  * Copyright (c) 2018 LSI-TEC - Caninos Loucos
  12  * Author: Edgar Bernardi Righi <edgar.righi@lsitec.org.br>
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/platform_device.h>
  17
  18 #include "owl-common.h"
  19 #include "owl-composite.h"
  20 #include "owl-divider.h"
  21 #include "owl-factor.h"
  22 #include "owl-fixed-factor.h"
  23 #include "owl-gate.h"
  24 #include "owl-mux.h"
  25 #include "owl-pll.h"
  26
  27 #include <dt-bindings/clock/actions,s500-cmu.h>
  28
  29 #define CMU_COREPLL                     (0x0000)
  30 #define CMU_DEVPLL                      (0x0004)
  31 #define CMU_DDRPLL                      (0x0008)
  32 #define CMU_NANDPLL                     (0x000C)
  33 #define CMU_DISPLAYPLL                  (0x0010)
  34 #define CMU_AUDIOPLL                    (0x0014)
  35 #define CMU_TVOUTPLL                    (0x0018)
  36 #define CMU_BUSCLK                      (0x001C)
  37 #define CMU_SENSORCLK                   (0x0020)
  38 #define CMU_LCDCLK                      (0x0024)
  39 #define CMU_DSICLK                      (0x0028)
  40 #define CMU_CSICLK                      (0x002C)
  41 #define CMU_DECLK                       (0x0030)
  42 #define CMU_BISPCLK                     (0x0034)
  43 #define CMU_BUSCLK1                     (0x0038)
  44 #define CMU_VDECLK                      (0x0040)
  45 #define CMU_VCECLK                      (0x0044)
  46 #define CMU_NANDCCLK                    (0x004C)
  47 #define CMU_SD0CLK                      (0x0050)
  48 #define CMU_SD1CLK                      (0x0054)
  49 #define CMU_SD2CLK                      (0x0058)
  50 #define CMU_UART0CLK                    (0x005C)
  51 #define CMU_UART1CLK                    (0x0060)
  52 #define CMU_UART2CLK                    (0x0064)
  53 #define CMU_PWM4CLK                     (0x0068)
  54 #define CMU_PWM5CLK                     (0x006C)
  55 #define CMU_PWM0CLK                     (0x0070)
  56 #define CMU_PWM1CLK                     (0x0074)
  57 #define CMU_PWM2CLK                     (0x0078)
  58 #define CMU_PWM3CLK                     (0x007C)
  59 #define CMU_USBPLL                      (0x0080)
  60 #define CMU_ETHERNETPLL                 (0x0084)
  61 #define CMU_CVBSPLL                     (0x0088)
  62 #define CMU_LENSCLK                     (0x008C)
  63 #define CMU_GPU3DCLK                    (0x0090)
  64 #define CMU_CORECTL                     (0x009C)
  65 #define CMU_DEVCLKEN0                   (0x00A0)
  66 #define CMU_DEVCLKEN1                   (0x00A4)
  67 #define CMU_DEVRST0                     (0x00A8)
  68 #define CMU_DEVRST1                     (0x00AC)
  69 #define CMU_UART3CLK                    (0x00B0)
  70 #define CMU_UART4CLK                    (0x00B4)
  71 #define CMU_UART5CLK                    (0x00B8)
  72 #define CMU_UART6CLK                    (0x00BC)
  73 #define CMU_SSCLK                       (0x00C0)
  74 #define CMU_DIGITALDEBUG                (0x00D0)
  75 #define CMU_ANALOGDEBUG                 (0x00D4)
  76 #define CMU_COREPLLDEBUG                (0x00D8)
  77 #define CMU_DEVPLLDEBUG                 (0x00DC)
  78 #define CMU_DDRPLLDEBUG                 (0x00E0)
  79 #define CMU_NANDPLLDEBUG                (0x00E4)
  80 #define CMU_DISPLAYPLLDEBUG             (0x00E8)
  81 #define CMU_TVOUTPLLDEBUG               (0x00EC)
  82 #define CMU_DEEPCOLORPLLDEBUG           (0x00F4)
  83 #define CMU_AUDIOPLL_ETHPLLDEBUG        (0x00F8)
  84 #define CMU_CVBSPLLDEBUG                (0x00FC)
  85
  86 #define OWL_S500_COREPLL_DELAY          (150)
  87 #define OWL_S500_DDRPLL_DELAY           (63)
  88 #define OWL_S500_DEVPLL_DELAY           (28)
  89 #define OWL_S500_NANDPLL_DELAY          (44)
  90 #define OWL_S500_DISPLAYPLL_DELAY       (57)
  91 #define OWL_S500_ETHERNETPLL_DELAY      (25)
  92 #define OWL_S500_AUDIOPLL_DELAY         (100)
  93
  94 static const struct clk_pll_table clk_audio_pll_table[] = {
  95         { 0, 45158400 }, { 1, 49152000 },
  96         { 0, 0 },
  97 };
  98
  99 /* pll clocks */
 100 static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
 101 static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk", CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
 102 static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
 103 static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
 104 static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
 105 static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
 106 static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED);
 107
 108 static const char * const dev_clk_mux_p[] = { "hosc", "dev_pll_clk" };
 109 static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
 110 static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
 111 static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
 112 static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
 113 static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
 114 static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
 115 static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
 116 static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
 117 static const char * const hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
 118 static const char * const nand_clk_mux_p[] = { "nand_pll_clk", "display_pll_clk", "dev_clk", "ddr_pll_clk" };
 119
 120 static struct clk_factor_table sd_factor_table[] = {
 121         /* bit0 ~ 4 */
 122         { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
 123         { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
 124         { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
 125         { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
 126         { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
 127         { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
 128         { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
 129         { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
 130
 131         /* bit8: /128 */
 132         { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
 133         { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
 134         { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
 135         { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
 136         { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
 137         { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
 138         { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
 139         { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
 140         { 0, 0, 0 },
 141 };
 142
 143 static struct clk_factor_table bisp_factor_table[] = {
 144         { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
 145         { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
 146         { 0, 0, 0 },
 147 };
 148
 149 static struct clk_factor_table ahb_factor_table[] = {
 150         { 1, 1, 2 }, { 2, 1, 3 },
 151         { 0, 0, 0 },
 152 };
 153
 154 static struct clk_div_table rmii_ref_div_table[] = {
 155         { 0, 4 }, { 1, 10 },
 156         { 0, 0 },
 157 };
 158
 159 static struct clk_div_table i2s_div_table[] = {
 160         { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
 161         { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
 162         { 8, 24 },
 163         { 0, 0 },
 164 };
 165
 166 static struct clk_div_table nand_div_table[] = {
 167         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
 168         { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
 169         { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
 170         { 0, 0 },
 171 };
 172
 173 /* mux clock */
 174 static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
 175 static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
 176
 177 /* gate clocks */
 178 static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
 179 static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
 180 static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
 181 static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
 182 static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
 183 static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
 184
 185 /* divider clocks */
 186 static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
 187 static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
 188
 189 /* factor clocks */
 190 static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
 191 static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
 192 static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
 193
 194 /* composite clocks */
 195 static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
 196                         OWL_MUX_HW(CMU_VCECLK, 4, 2),
 197                         OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
 198                         OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
 199                         0);
 200
 201 static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
 202                         OWL_MUX_HW(CMU_VDECLK, 4, 2),
 203                         OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
 204                         OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
 205                         0);
 206
 207 static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
 208                         OWL_MUX_HW(CMU_BISPCLK, 4, 1),
 209                         OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
 210                         OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
 211                         0);
 212
 213 static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
 214                         OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
 215                         OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
 216                         OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table),
 217                         CLK_IGNORE_UNUSED);
 218
 219 static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
 220                         OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
 221                         OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
 222                         OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table),
 223                         CLK_IGNORE_UNUSED);
 224
 225 static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
 226                         OWL_MUX_HW(CMU_SD0CLK, 9, 1),
 227                         OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
 228                         OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
 229                         0);
 230
 231 static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
 232                         OWL_MUX_HW(CMU_SD1CLK, 9, 1),
 233                         OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
 234                         OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
 235                         0);
 236
 237 static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
 238                         OWL_MUX_HW(CMU_SD2CLK, 9, 1),
 239                         OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
 240                         OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
 241                         0);
 242
 243 static OWL_COMP_DIV(pwm0_clk, "pwm0_clk", pwm_clk_mux_p,
 244                         OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
 245                         OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
 246                         OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
 247                         0);
 248
 249 static OWL_COMP_DIV(pwm1_clk, "pwm1_clk", pwm_clk_mux_p,
 250                         OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
 251                         OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
 252                         OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
 253                         0);
 254
 255 static OWL_COMP_DIV(pwm2_clk, "pwm2_clk", pwm_clk_mux_p,
 256                         OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
 257                         OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
 258                         OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
 259                         0);
 260
 261 static OWL_COMP_DIV(pwm3_clk, "pwm3_clk", pwm_clk_mux_p,
 262                         OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
 263                         OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
 264                         OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
 265                         0);
 266
 267 static OWL_COMP_DIV(pwm4_clk, "pwm4_clk", pwm_clk_mux_p,
 268                         OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
 269                         OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
 270                         OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
 271                         0);
 272
 273 static OWL_COMP_DIV(pwm5_clk, "pwm5_clk", pwm_clk_mux_p,
 274                         OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
 275                         OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
 276                         OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
 277                         0);
 278
 279 static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
 280                         OWL_MUX_HW(CMU_DECLK, 12, 1),
 281                         OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
 282                         0);
 283
 284 static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "ethernet_pll_clk",
 285                         OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
 286                         1, 5, 0);
 287
 288 static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "ethernet_pll_clk",
 289                         OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
 290                         1, 5, 0);
 291
 292 static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "ethernet_pll_clk",
 293                         OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
 294                         1, 5, 0);
 295
 296 static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
 297                         OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
 298                         1, 5, 0);
 299
 300 static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
 301                         OWL_MUX_HW(CMU_UART0CLK, 16, 1),
 302                         OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
 303                         OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 304                         CLK_IGNORE_UNUSED);
 305
 306 static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
 307                         OWL_MUX_HW(CMU_UART1CLK, 16, 1),
 308                         OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
 309                         OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 310                         CLK_IGNORE_UNUSED);
 311
 312 static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
 313                         OWL_MUX_HW(CMU_UART2CLK, 16, 1),
 314                         OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
 315                         OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 316                         CLK_IGNORE_UNUSED);
 317
 318 static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
 319                         OWL_MUX_HW(CMU_UART3CLK, 16, 1),
 320                         OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
 321                         OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 322                         CLK_IGNORE_UNUSED);
 323
 324 static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
 325                         OWL_MUX_HW(CMU_UART4CLK, 16, 1),
 326                         OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
 327                         OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 328                         CLK_IGNORE_UNUSED);
 329
 330 static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
 331                         OWL_MUX_HW(CMU_UART5CLK, 16, 1),
 332                         OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
 333                         OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 334                         CLK_IGNORE_UNUSED);
 335
 336 static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
 337                         OWL_MUX_HW(CMU_UART6CLK, 16, 1),
 338                         OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
 339                         OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
 340                         CLK_IGNORE_UNUSED);
 341
 342 static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
 343                         OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
 344                         OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
 345                         OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
 346                         0);
 347
 348 static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
 349                         OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
 350                         OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
 351                         OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
 352                         0);
 353
 354 static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
 355                         OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
 356                         OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
 357                         OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
 358                         0);
 359
 360 static OWL_COMP_DIV(spdif_clk, "spdif_clk", i2s_clk_mux_p,
 361                         OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
 362                         OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
 363                         OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
 364                         0);
 365
 366 static OWL_COMP_DIV(nand_clk, "nand_clk", nand_clk_mux_p,
 367                         OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
 368                         OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
 369                         OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
 370                         CLK_SET_RATE_PARENT);
 371
 372 static OWL_COMP_DIV(ecc_clk, "ecc_clk", nand_clk_mux_p,
 373                         OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
 374                         OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
 375                         OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),
 376                         CLK_SET_RATE_PARENT);
 377
 378 static struct owl_clk_common *s500_clks[] = {
 379         &ethernet_pll_clk.common,
 380         &core_pll_clk.common,
 381         &ddr_pll_clk.common,
 382         &dev_pll_clk.common,
 383         &nand_pll_clk.common,
 384         &audio_pll_clk.common,
 385         &display_pll_clk.common,
 386         &dev_clk.common,
 387         &timer_clk.common,
 388         &i2c0_clk.common,
 389         &i2c1_clk.common,
 390         &i2c2_clk.common,
 391         &i2c3_clk.common,
 392         &uart0_clk.common,
 393         &uart1_clk.common,
 394         &uart2_clk.common,
 395         &uart3_clk.common,
 396         &uart4_clk.common,
 397         &uart5_clk.common,
 398         &uart6_clk.common,
 399         &pwm0_clk.common,
 400         &pwm1_clk.common,
 401         &pwm2_clk.common,
 402         &pwm3_clk.common,
 403         &pwm4_clk.common,
 404         &pwm5_clk.common,
 405         &sensor0_clk.common,
 406         &sensor1_clk.common,
 407         &sd0_clk.common,
 408         &sd1_clk.common,
 409         &sd2_clk.common,
 410         &bisp_clk.common,
 411         &ahb_clk.common,
 412         &ahbprediv_clk.common,
 413         &h_clk.common,
 414         &spi0_clk.common,
 415         &spi1_clk.common,
 416         &spi2_clk.common,
 417         &spi3_clk.common,
 418         &rmii_ref_clk.common,
 419         &de_clk.common,
 420         &de1_clk.common,
 421         &de2_clk.common,
 422         &i2srx_clk.common,
 423         &i2stx_clk.common,
 424         &hdmia_clk.common,
 425         &hdmi_clk.common,
 426         &vce_clk.common,
 427         &vde_clk.common,
 428         &spdif_clk.common,
 429         &nand_clk.common,
 430         &ecc_clk.common,
 431 };
 432
 433 static struct clk_hw_onecell_data s500_hw_clks = {
 434         .hws = {
 435                 [CLK_ETHERNET_PLL]      = &ethernet_pll_clk.common.hw,
 436                 [CLK_CORE_PLL]          = &core_pll_clk.common.hw,
 437                 [CLK_DDR_PLL]           = &ddr_pll_clk.common.hw,
 438                 [CLK_NAND_PLL]          = &nand_pll_clk.common.hw,
 439                 [CLK_DISPLAY_PLL]       = &display_pll_clk.common.hw,
 440                 [CLK_DEV_PLL]           = &dev_pll_clk.common.hw,
 441                 [CLK_AUDIO_PLL]         = &audio_pll_clk.common.hw,
 442                 [CLK_TIMER]             = &timer_clk.common.hw,
 443                 [CLK_DEV]               = &dev_clk.common.hw,
 444                 [CLK_DE]                = &de_clk.common.hw,
 445                 [CLK_DE1]               = &de1_clk.common.hw,
 446                 [CLK_DE2]               = &de2_clk.common.hw,
 447                 [CLK_I2C0]              = &i2c0_clk.common.hw,
 448                 [CLK_I2C1]              = &i2c1_clk.common.hw,
 449                 [CLK_I2C2]              = &i2c2_clk.common.hw,
 450                 [CLK_I2C3]              = &i2c3_clk.common.hw,
 451                 [CLK_I2SRX]             = &i2srx_clk.common.hw,
 452                 [CLK_I2STX]             = &i2stx_clk.common.hw,
 453                 [CLK_UART0]             = &uart0_clk.common.hw,
 454                 [CLK_UART1]             = &uart1_clk.common.hw,
 455                 [CLK_UART2]             = &uart2_clk.common.hw,
 456                 [CLK_UART3]             = &uart3_clk.common.hw,
 457                 [CLK_UART4]             = &uart4_clk.common.hw,
 458                 [CLK_UART5]             = &uart5_clk.common.hw,
 459                 [CLK_UART6]             = &uart6_clk.common.hw,
 460                 [CLK_PWM0]              = &pwm0_clk.common.hw,
 461                 [CLK_PWM1]              = &pwm1_clk.common.hw,
 462                 [CLK_PWM2]              = &pwm2_clk.common.hw,
 463                 [CLK_PWM3]              = &pwm3_clk.common.hw,
 464                 [CLK_PWM4]              = &pwm4_clk.common.hw,
 465                 [CLK_PWM5]              = &pwm5_clk.common.hw,
 466                 [CLK_SENSOR0]           = &sensor0_clk.common.hw,
 467                 [CLK_SENSOR1]           = &sensor1_clk.common.hw,
 468                 [CLK_SD0]               = &sd0_clk.common.hw,
 469                 [CLK_SD1]               = &sd1_clk.common.hw,
 470                 [CLK_SD2]               = &sd2_clk.common.hw,
 471                 [CLK_BISP]              = &bisp_clk.common.hw,
 472                 [CLK_SPI0]              = &spi0_clk.common.hw,
 473                 [CLK_SPI1]              = &spi1_clk.common.hw,
 474                 [CLK_SPI2]              = &spi2_clk.common.hw,
 475                 [CLK_SPI3]              = &spi3_clk.common.hw,
 476                 [CLK_AHB]               = &ahb_clk.common.hw,
 477                 [CLK_H]                 = &h_clk.common.hw,
 478                 [CLK_AHBPREDIV]         = &ahbprediv_clk.common.hw,
 479                 [CLK_RMII_REF]          = &rmii_ref_clk.common.hw,
 480                 [CLK_HDMI_AUDIO]        = &hdmia_clk.common.hw,
 481                 [CLK_HDMI]              = &hdmi_clk.common.hw,
 482                 [CLK_VDE]               = &vde_clk.common.hw,
 483                 [CLK_VCE]               = &vce_clk.common.hw,
 484                 [CLK_SPDIF]             = &spdif_clk.common.hw,
 485                 [CLK_NAND]              = &nand_clk.common.hw,
 486                 [CLK_ECC]               = &ecc_clk.common.hw,
 487         },
 488         .num = CLK_NR_CLKS,
 489 };
 490
 491 static struct owl_clk_desc s500_clk_desc = {
 492         .clks       = s500_clks,
 493         .num_clks   = ARRAY_SIZE(s500_clks),
 494
 495         .hw_clks    = &s500_hw_clks,
 496 };
 497
 498 static int s500_clk_probe(struct platform_device *pdev)
 499 {
 500         struct owl_clk_desc *desc;
 501
 502         desc = &s500_clk_desc;
 503         owl_clk_regmap_init(pdev, desc);
 504
 505         return owl_clk_probe(&pdev->dev, desc->hw_clks);
 506 }
 507
 508 static const struct of_device_id s500_clk_of_match[] = {
 509         { .compatible = "actions,s500-cmu", },
 510         { /* sentinel */ }
 511 };
 512
 513 static struct platform_driver s500_clk_driver = {
 514         .probe = s500_clk_probe,
 515         .driver = {
 516                 .name = "s500-cmu",
 517                 .of_match_table = s500_clk_of_match,
 518         },
 519 };
 520
 521 static int __init s500_clk_init(void)
 522 {
 523         return platform_driver_register(&s500_clk_driver);
 524 }
 525 core_initcall(s500_clk_init);