2 * (C) Copyright 2002-2004
3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
7 * Modified to work with AMD flashes
11 * Modified to work with little-endian systems.
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * 01/20/2004 - combined variants of original driver.
33 * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
34 * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
35 * 01/27/2004 - Little endian support Ed Okerson
37 * Tested Architectures
38 * Port Width Chip Width # of banks Flash Chip Board
39 * 32 16 1 28F128J3 seranoa/eagle
40 * 64 16 1 28F128J3 seranoa/falcon
44 /* The DEBUG define must be before common to enable debugging */
48 #include <asm/processor.h>
49 #include <asm/byteorder.h>
50 #include <environment.h>
51 #ifdef CFG_FLASH_CFI_DRIVER
54 * This file implements a Common Flash Interface (CFI) driver for U-Boot.
55 * The width of the port and the width of the chips are determined at initialization.
56 * These widths are used to calculate the address for access CFI data structures.
57 * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
60 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
61 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
62 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
63 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
67 * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
68 * Table (ALT) to determine if protection is available
70 * Add support for other command sets Use the PRI and ALT to determine command set
71 * Verify erase and program timeouts.
74 #ifndef CFG_FLASH_BANKS_LIST
75 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
78 #define FLASH_CMD_CFI 0x98
79 #define FLASH_CMD_READ_ID 0x90
80 #define FLASH_CMD_RESET 0xff
81 #define FLASH_CMD_BLOCK_ERASE 0x20
82 #define FLASH_CMD_ERASE_CONFIRM 0xD0
83 #define FLASH_CMD_WRITE 0x40
84 #define FLASH_CMD_PROTECT 0x60
85 #define FLASH_CMD_PROTECT_SET 0x01
86 #define FLASH_CMD_PROTECT_CLEAR 0xD0
87 #define FLASH_CMD_CLEAR_STATUS 0x50
88 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8
89 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
91 #define FLASH_STATUS_DONE 0x80
92 #define FLASH_STATUS_ESS 0x40
93 #define FLASH_STATUS_ECLBS 0x20
94 #define FLASH_STATUS_PSLBS 0x10
95 #define FLASH_STATUS_VPENS 0x08
96 #define FLASH_STATUS_PSS 0x04
97 #define FLASH_STATUS_DPS 0x02
98 #define FLASH_STATUS_R 0x01
99 #define FLASH_STATUS_PROTECT 0x01
101 #define AMD_CMD_RESET 0xF0
102 #define AMD_CMD_WRITE 0xA0
103 #define AMD_CMD_ERASE_START 0x80
104 #define AMD_CMD_ERASE_SECTOR 0x30
105 #define AMD_CMD_UNLOCK_START 0xAA
106 #define AMD_CMD_UNLOCK_ACK 0x55
107 #define AMD_CMD_WRITE_TO_BUFFER 0x25
108 #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
110 #define AMD_STATUS_TOGGLE 0x40
111 #define AMD_STATUS_ERROR 0x20
113 #define AMD_ADDR_ERASE_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
114 #define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
115 #define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA)
117 #define FLASH_OFFSET_CFI 0x55
118 #define FLASH_OFFSET_CFI_RESP 0x10
119 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13
120 #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 /* extended query table primary addr */
121 #define FLASH_OFFSET_WTOUT 0x1F
122 #define FLASH_OFFSET_WBTOUT 0x20
123 #define FLASH_OFFSET_ETOUT 0x21
124 #define FLASH_OFFSET_CETOUT 0x22
125 #define FLASH_OFFSET_WMAX_TOUT 0x23
126 #define FLASH_OFFSET_WBMAX_TOUT 0x24
127 #define FLASH_OFFSET_EMAX_TOUT 0x25
128 #define FLASH_OFFSET_CEMAX_TOUT 0x26
129 #define FLASH_OFFSET_SIZE 0x27
130 #define FLASH_OFFSET_INTERFACE 0x28
131 #define FLASH_OFFSET_BUFFER_SIZE 0x2A
132 #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
133 #define FLASH_OFFSET_ERASE_REGIONS 0x2D
134 #define FLASH_OFFSET_PROTECT 0x02
135 #define FLASH_OFFSET_USER_PROTECTION 0x85
136 #define FLASH_OFFSET_INTEL_PROTECTION 0x81
139 #define FLASH_MAN_CFI 0x01000000
141 #define CFI_CMDSET_NONE 0
142 #define CFI_CMDSET_INTEL_EXTENDED 1
143 #define CFI_CMDSET_AMD_STANDARD 2
144 #define CFI_CMDSET_INTEL_STANDARD 3
145 #define CFI_CMDSET_AMD_EXTENDED 4
146 #define CFI_CMDSET_MITSU_STANDARD 256
147 #define CFI_CMDSET_MITSU_EXTENDED 257
148 #define CFI_CMDSET_SST 258
151 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
152 # undef FLASH_CMD_RESET
153 # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
161 unsigned long long ll;
165 volatile unsigned char *cp;
166 volatile unsigned short *wp;
167 volatile unsigned long *lp;
168 volatile unsigned long long *llp;
171 #define NUM_ERASE_REGIONS 4
173 /* use CFG_MAX_FLASH_BANKS_DETECT if defined */
174 #ifdef CFG_MAX_FLASH_BANKS_DETECT
175 static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
176 flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
178 static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
179 flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
183 * Check if chip width is defined. If not, start detecting with 8bit.
185 #ifndef CFG_FLASH_CFI_WIDTH
186 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
190 /*-----------------------------------------------------------------------
194 typedef unsigned long flash_sect_t;
196 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
197 static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
198 static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
199 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
200 static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
201 static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
202 static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
203 static int flash_detect_cfi (flash_info_t * info);
204 static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
205 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
206 ulong tout, char *prompt);
207 ulong flash_get_size (ulong base, int banknum);
208 #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
209 static flash_info_t *flash_get_info(ulong base);
211 #ifdef CFG_FLASH_USE_BUFFER_WRITE
212 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
215 /*-----------------------------------------------------------------------
216 * create an address based on the offset and the port width
218 inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
220 return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
224 /*-----------------------------------------------------------------------
227 void print_longlong (char *str, unsigned long long data)
232 cp = (unsigned char *) &data;
233 for (i = 0; i < 8; i++)
234 sprintf (&str[i * 2], "%2.2x", *cp++);
236 static void flash_printqry (flash_info_t * info, flash_sect_t sect)
241 for (x = 0; x < 0x40; x += 16U / info->portwidth) {
243 flash_make_addr (info, sect,
244 x + FLASH_OFFSET_CFI_RESP);
245 debug ("%p : ", cptr.cp);
246 for (y = 0; y < 16; y++) {
247 debug ("%2.2x ", cptr.cp[y]);
250 for (y = 0; y < 16; y++) {
251 if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
252 debug ("%c", cptr.cp[y]);
263 /*-----------------------------------------------------------------------
264 * read a character at a port width address
266 inline uchar flash_read_uchar (flash_info_t * info, uint offset)
270 cp = flash_make_addr (info, 0, offset);
271 #if defined(__LITTLE_ENDIAN)
274 return (cp[info->portwidth - 1]);
278 /*-----------------------------------------------------------------------
279 * read a short word by swapping for ppc format.
281 ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
289 addr = flash_make_addr (info, sect, offset);
292 debug ("ushort addr is at %p info->portwidth = %d\n", addr,
294 for (x = 0; x < 2 * info->portwidth; x++) {
295 debug ("addr[%x] = 0x%x\n", x, addr[x]);
298 #if defined(__LITTLE_ENDIAN)
299 retval = ((addr[(info->portwidth)] << 8) | addr[0]);
301 retval = ((addr[(2 * info->portwidth) - 1] << 8) |
302 addr[info->portwidth - 1]);
305 debug ("retval = 0x%x\n", retval);
309 /*-----------------------------------------------------------------------
310 * read a long word by picking the least significant byte of each maiximum
311 * port size word. Swap for ppc format.
313 ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
321 addr = flash_make_addr (info, sect, offset);
324 debug ("long addr is at %p info->portwidth = %d\n", addr,
326 for (x = 0; x < 4 * info->portwidth; x++) {
327 debug ("addr[%x] = 0x%x\n", x, addr[x]);
330 #if defined(__LITTLE_ENDIAN)
331 retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
332 (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
334 retval = (addr[(2 * info->portwidth) - 1] << 24) |
335 (addr[(info->portwidth) - 1] << 16) |
336 (addr[(4 * info->portwidth) - 1] << 8) |
337 addr[(3 * info->portwidth) - 1];
343 /*-----------------------------------------------------------------------
345 unsigned long flash_init (void)
347 unsigned long size = 0;
350 #ifdef CFG_FLASH_PROTECTION
351 char *s = getenv("unlock");
354 /* Init: no FLASHes known */
355 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
356 flash_info[i].flash_id = FLASH_UNKNOWN;
357 size += flash_info[i].size = flash_get_size (bank_base[i], i);
358 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
359 #ifndef CFG_FLASH_QUIET_TEST
360 printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
361 i, flash_info[i].size, flash_info[i].size << 20);
362 #endif /* CFG_FLASH_QUIET_TEST */
364 #ifdef CFG_FLASH_PROTECTION
365 else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
367 * Only the U-Boot image and it's environment is protected,
368 * all other sectors are unprotected (unlocked) if flash
369 * hardware protection is used (CFG_FLASH_PROTECTION) and
370 * the environment variable "unlock" is set to "yes".
372 if (flash_info[i].legacy_unlock) {
376 * Disable legacy_unlock temporarily, since
377 * flash_real_protect would relock all other sectors
380 flash_info[i].legacy_unlock = 0;
383 * Legacy unlocking (e.g. Intel J3) -> unlock only one
384 * sector. This will unlock all sectors.
386 flash_real_protect (&flash_info[i], 0, 0);
388 flash_info[i].legacy_unlock = 1;
391 * Manually mark other sectors as unlocked (unprotected)
393 for (k = 1; k < flash_info[i].sector_count; k++)
394 flash_info[i].protect[k] = 0;
397 * No legancy unlocking -> unlock all sectors
399 flash_protect (FLAG_PROTECT_CLEAR,
400 flash_info[i].start[0],
401 flash_info[i].start[0] + flash_info[i].size - 1,
405 #endif /* CFG_FLASH_PROTECTION */
408 /* Monitor protection ON by default */
409 #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
410 flash_protect (FLAG_PROTECT_SET,
412 CFG_MONITOR_BASE + monitor_flash_len - 1,
413 flash_get_info(CFG_MONITOR_BASE));
416 /* Environment protection ON by default */
417 #ifdef CFG_ENV_IS_IN_FLASH
418 flash_protect (FLAG_PROTECT_SET,
420 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
421 flash_get_info(CFG_ENV_ADDR));
424 /* Redundant environment protection ON by default */
425 #ifdef CFG_ENV_ADDR_REDUND
426 flash_protect (FLAG_PROTECT_SET,
428 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
429 flash_get_info(CFG_ENV_ADDR_REDUND));
434 /*-----------------------------------------------------------------------
436 #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
437 static flash_info_t *flash_get_info(ulong base)
440 flash_info_t * info = 0;
442 for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
443 info = & flash_info[i];
444 if (info->size && info->start[0] <= base &&
445 base <= info->start[0] + info->size - 1)
449 return i == CFG_MAX_FLASH_BANKS ? 0 : info;
453 /*-----------------------------------------------------------------------
455 int flash_erase (flash_info_t * info, int s_first, int s_last)
461 if (info->flash_id != FLASH_MAN_CFI) {
462 puts ("Can't erase unknown flash type - aborted\n");
465 if ((s_first < 0) || (s_first > s_last)) {
466 puts ("- no sectors to erase\n");
471 for (sect = s_first; sect <= s_last; ++sect) {
472 if (info->protect[sect]) {
477 printf ("- Warning: %d protected sectors will not be erased!\n", prot);
483 for (sect = s_first; sect <= s_last; sect++) {
484 if (info->protect[sect] == 0) { /* not protected */
485 switch (info->vendor) {
486 case CFI_CMDSET_INTEL_STANDARD:
487 case CFI_CMDSET_INTEL_EXTENDED:
488 flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
489 flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
490 flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
492 case CFI_CMDSET_AMD_STANDARD:
493 case CFI_CMDSET_AMD_EXTENDED:
494 flash_unlock_seq (info, sect);
495 flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
496 AMD_CMD_ERASE_START);
497 flash_unlock_seq (info, sect);
498 flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
501 debug ("Unkown flash vendor %d\n",
506 if (flash_full_status_check
507 (info, sect, info->erase_blk_tout, "erase")) {
517 /*-----------------------------------------------------------------------
519 void flash_print_info (flash_info_t * info)
523 if (info->flash_id != FLASH_MAN_CFI) {
524 puts ("missing or unknown FLASH type\n");
528 printf ("CFI conformant FLASH (%d x %d)",
529 (info->portwidth << 3), (info->chipwidth << 3));
530 printf (" Size: %ld MB in %d Sectors\n",
531 info->size >> 20, info->sector_count);
532 printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
533 info->erase_blk_tout,
535 info->buffer_write_tout,
538 puts (" Sector Start Addresses:");
539 for (i = 0; i < info->sector_count; ++i) {
540 #ifdef CFG_FLASH_EMPTY_INFO
544 volatile unsigned long *flash;
547 * Check if whole sector is erased
549 if (i != (info->sector_count - 1))
550 size = info->start[i + 1] - info->start[i];
552 size = info->start[0] + info->size - info->start[i];
554 flash = (volatile unsigned long *) info->start[i];
555 size = size >> 2; /* divide by 4 for longword access */
556 for (k = 0; k < size; k++) {
557 if (*flash++ != 0xffffffff) {
565 /* print empty and read-only info */
566 printf (" %08lX%s%s",
569 info->protect[i] ? "RO " : " ");
570 #else /* ! CFG_FLASH_EMPTY_INFO */
574 info->start[i], info->protect[i] ? " (RO)" : " ");
581 /*-----------------------------------------------------------------------
582 * Copy memory to flash, returns:
585 * 2 - Flash not erased
587 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
595 #ifdef CFG_FLASH_USE_BUFFER_WRITE
598 /* get lower aligned address */
599 /* get lower aligned address */
600 wp = (addr & ~(info->portwidth - 1));
602 /* handle unaligned start */
603 if ((aln = addr - wp) != 0) {
606 for (i = 0; i < aln; ++i, ++cp)
607 flash_add_byte (info, &cword, (*(uchar *) cp));
609 for (; (i < info->portwidth) && (cnt > 0); i++) {
610 flash_add_byte (info, &cword, *src++);
614 for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
615 flash_add_byte (info, &cword, (*(uchar *) cp));
616 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
621 /* handle the aligned part */
622 #ifdef CFG_FLASH_USE_BUFFER_WRITE
623 buffered_size = (info->portwidth / info->chipwidth);
624 buffered_size *= info->buffer_size;
625 while (cnt >= info->portwidth) {
626 /* prohibit buffer write when buffer_size is 1 */
627 if (info->buffer_size == 1) {
629 for (i = 0; i < info->portwidth; i++)
630 flash_add_byte (info, &cword, *src++);
631 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
633 wp += info->portwidth;
634 cnt -= info->portwidth;
638 /* write buffer until next buffered_size aligned boundary */
639 i = buffered_size - (wp % buffered_size);
642 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
644 i -= i & (info->portwidth - 1);
650 while (cnt >= info->portwidth) {
652 for (i = 0; i < info->portwidth; i++) {
653 flash_add_byte (info, &cword, *src++);
655 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
657 wp += info->portwidth;
658 cnt -= info->portwidth;
660 #endif /* CFG_FLASH_USE_BUFFER_WRITE */
666 * handle unaligned tail bytes
669 for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
670 flash_add_byte (info, &cword, *src++);
673 for (; i < info->portwidth; ++i, ++cp) {
674 flash_add_byte (info, &cword, (*(uchar *) cp));
677 return flash_write_cfiword (info, wp, cword);
680 /*-----------------------------------------------------------------------
682 #ifdef CFG_FLASH_PROTECTION
684 int flash_real_protect (flash_info_t * info, long sector, int prot)
688 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
689 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
691 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
693 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
696 flash_full_status_check (info, sector, info->erase_blk_tout,
697 prot ? "protect" : "unprotect")) == 0) {
699 info->protect[sector] = prot;
702 * On some of Intel's flash chips (marked via legacy_unlock)
703 * unprotect unprotects all locking.
705 if ((prot == 0) && (info->legacy_unlock)) {
708 for (i = 0; i < info->sector_count; i++) {
709 if (info->protect[i])
710 flash_real_protect (info, i, 1);
717 /*-----------------------------------------------------------------------
718 * flash_read_user_serial - read the OneTimeProgramming cells
720 void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
727 src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
728 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
729 memcpy (dst, src + offset, len);
730 flash_write_cmd (info, 0, 0, info->cmd_reset);
734 * flash_read_factory_serial - read the device Id from the protection area
736 void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
741 src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
742 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
743 memcpy (buffer, src + offset, len);
744 flash_write_cmd (info, 0, 0, info->cmd_reset);
747 #endif /* CFG_FLASH_PROTECTION */
750 * flash_is_busy - check to see if the flash is busy
751 * This routine checks the status of the chip and returns true if the chip is busy
753 static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
757 switch (info->vendor) {
758 case CFI_CMDSET_INTEL_STANDARD:
759 case CFI_CMDSET_INTEL_EXTENDED:
760 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
762 case CFI_CMDSET_AMD_STANDARD:
763 case CFI_CMDSET_AMD_EXTENDED:
764 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
769 debug ("flash_is_busy: %d\n", retval);
773 /*-----------------------------------------------------------------------
774 * wait for XSR.7 to be set. Time out with an error if it does not.
775 * This routine does not set the flash to read-array mode.
777 static int flash_status_check (flash_info_t * info, flash_sect_t sector,
778 ulong tout, char *prompt)
786 /* Wait for command completion */
787 start = get_timer (0);
788 while (flash_is_busy (info, sector)) {
789 if (get_timer (start) > tout) {
790 printf ("Flash %s timeout at address %lx data %lx\n",
791 prompt, info->start[sector],
792 flash_read_long (info, sector, 0));
793 flash_write_cmd (info, sector, 0, info->cmd_reset);
800 /*-----------------------------------------------------------------------
801 * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
802 * This routine sets the flash to read-array mode.
804 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
805 ulong tout, char *prompt)
809 retcode = flash_status_check (info, sector, tout, prompt);
810 switch (info->vendor) {
811 case CFI_CMDSET_INTEL_EXTENDED:
812 case CFI_CMDSET_INTEL_STANDARD:
813 if ((retcode == ERR_OK)
814 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
816 printf ("Flash %s error at address %lx\n", prompt,
817 info->start[sector]);
818 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
819 puts ("Command Sequence Error.\n");
820 } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
821 puts ("Block Erase Error.\n");
822 retcode = ERR_NOT_ERASED;
823 } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
824 puts ("Locking Error\n");
826 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
827 puts ("Block locked.\n");
828 retcode = ERR_PROTECTED;
830 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
831 puts ("Vpp Low Error.\n");
833 flash_write_cmd (info, sector, 0, info->cmd_reset);
841 /*-----------------------------------------------------------------------
843 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
845 #if defined(__LITTLE_ENDIAN)
848 unsigned long long ll;
851 switch (info->portwidth) {
855 case FLASH_CFI_16BIT:
856 #if defined(__LITTLE_ENDIAN)
859 cword->w = (cword->w >> 8) | w;
861 cword->w = (cword->w << 8) | c;
864 case FLASH_CFI_32BIT:
865 #if defined(__LITTLE_ENDIAN)
868 cword->l = (cword->l >> 8) | l;
870 cword->l = (cword->l << 8) | c;
873 case FLASH_CFI_64BIT:
874 #if defined(__LITTLE_ENDIAN)
877 cword->ll = (cword->ll >> 8) | ll;
879 cword->ll = (cword->ll << 8) | c;
886 /*-----------------------------------------------------------------------
887 * make a proper sized command based on the port and chip widths
889 static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
892 uchar *cp = (uchar *) cmdbuf;
894 #if defined(__LITTLE_ENDIAN)
895 for (i = info->portwidth; i > 0; i--)
897 for (i = 1; i <= info->portwidth; i++)
899 *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
903 * Write a proper sized command to the correct address
905 static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
908 volatile cfiptr_t addr;
911 addr.cp = flash_make_addr (info, sect, offset);
912 flash_make_cmd (info, cmd, &cword);
913 switch (info->portwidth) {
915 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
916 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
918 #ifdef CONFIG_BLACKFIN
922 case FLASH_CFI_16BIT:
923 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
925 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
927 #ifdef CONFIG_BLACKFIN
931 case FLASH_CFI_32BIT:
932 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
934 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
936 #ifdef CONFIG_BLACKFIN
940 case FLASH_CFI_64BIT:
945 print_longlong (str, cword.ll);
947 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
949 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
952 *addr.llp = cword.ll;
953 #ifdef CONFIG_BLACKFIN
960 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
962 flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
963 flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
966 /*-----------------------------------------------------------------------
968 static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
974 cptr.cp = flash_make_addr (info, sect, offset);
975 flash_make_cmd (info, cmd, &cword);
977 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
978 switch (info->portwidth) {
980 debug ("is= %x %x\n", cptr.cp[0], cword.c);
981 retval = (cptr.cp[0] == cword.c);
983 case FLASH_CFI_16BIT:
984 debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
985 retval = (cptr.wp[0] == cword.w);
987 case FLASH_CFI_32BIT:
988 debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
989 retval = (cptr.lp[0] == cword.l);
991 case FLASH_CFI_64BIT:
997 print_longlong (str1, cptr.llp[0]);
998 print_longlong (str2, cword.ll);
999 debug ("is= %s %s\n", str1, str2);
1002 retval = (cptr.llp[0] == cword.ll);
1011 /*-----------------------------------------------------------------------
1013 static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
1019 cptr.cp = flash_make_addr (info, sect, offset);
1020 flash_make_cmd (info, cmd, &cword);
1021 switch (info->portwidth) {
1022 case FLASH_CFI_8BIT:
1023 retval = ((cptr.cp[0] & cword.c) == cword.c);
1025 case FLASH_CFI_16BIT:
1026 retval = ((cptr.wp[0] & cword.w) == cword.w);
1028 case FLASH_CFI_32BIT:
1029 retval = ((cptr.lp[0] & cword.l) == cword.l);
1031 case FLASH_CFI_64BIT:
1032 retval = ((cptr.llp[0] & cword.ll) == cword.ll);
1041 /*-----------------------------------------------------------------------
1043 static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
1049 cptr.cp = flash_make_addr (info, sect, offset);
1050 flash_make_cmd (info, cmd, &cword);
1051 switch (info->portwidth) {
1052 case FLASH_CFI_8BIT:
1053 retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
1055 case FLASH_CFI_16BIT:
1056 retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
1058 case FLASH_CFI_32BIT:
1059 retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
1061 case FLASH_CFI_64BIT:
1062 retval = ((cptr.llp[0] & cword.ll) !=
1063 (cptr.llp[0] & cword.ll));
1072 /*-----------------------------------------------------------------------
1073 * detect if flash is compatible with the Common Flash Interface (CFI)
1074 * http://www.jedec.org/download/search/jesd68.pdf
1077 static int flash_detect_cfi (flash_info_t * info)
1079 debug ("flash detect cfi\n");
1081 for (info->portwidth = CFG_FLASH_CFI_WIDTH;
1082 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1083 for (info->chipwidth = FLASH_CFI_BY8;
1084 info->chipwidth <= info->portwidth;
1085 info->chipwidth <<= 1) {
1086 flash_write_cmd (info, 0, 0, info->cmd_reset);
1087 flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
1088 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
1089 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
1090 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
1091 info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
1092 debug ("device interface is %d\n",
1094 debug ("found port %d chip %d ",
1095 info->portwidth, info->chipwidth);
1096 debug ("port %d bits chip %d bits\n",
1097 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1098 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1103 debug ("not found\n");
1108 * The following code cannot be run from FLASH!
1111 ulong flash_get_size (ulong base, int banknum)
1113 flash_info_t *info = &flash_info[banknum];
1115 flash_sect_t sect_cnt;
1116 unsigned long sector;
1119 uchar num_erase_regions;
1120 int erase_region_size;
1121 int erase_region_count;
1122 #ifdef CFG_FLASH_PROTECTION
1124 info->legacy_unlock = 0;
1127 info->start[0] = base;
1129 if (flash_detect_cfi (info)) {
1130 info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
1132 flash_printqry (info, 0);
1134 switch (info->vendor) {
1135 case CFI_CMDSET_INTEL_STANDARD:
1136 case CFI_CMDSET_INTEL_EXTENDED:
1138 info->cmd_reset = FLASH_CMD_RESET;
1139 #ifdef CFG_FLASH_PROTECTION
1140 /* read legacy lock/unlock bit from intel flash */
1141 ext_addr = flash_read_ushort (info, 0,
1142 FLASH_OFFSET_EXT_QUERY_T_P_ADDR);
1143 info->legacy_unlock =
1144 flash_read_uchar (info, ext_addr + 5) & 0x08;
1147 case CFI_CMDSET_AMD_STANDARD:
1148 case CFI_CMDSET_AMD_EXTENDED:
1149 info->cmd_reset = AMD_CMD_RESET;
1153 debug ("manufacturer is %d\n", info->vendor);
1154 size_ratio = info->portwidth / info->chipwidth;
1155 /* if the chip is x8/x16 reduce the ratio by half */
1156 if ((info->interface == FLASH_CFI_X8X16)
1157 && (info->chipwidth == FLASH_CFI_BY8)) {
1160 num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
1161 debug ("size_ratio %d port %d bits chip %d bits\n",
1162 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1163 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1164 debug ("found %d erase regions\n", num_erase_regions);
1167 for (i = 0; i < num_erase_regions; i++) {
1168 if (i > NUM_ERASE_REGIONS) {
1169 printf ("%d erase regions found, only %d used\n",
1170 num_erase_regions, NUM_ERASE_REGIONS);
1173 tmp = flash_read_long (info, 0,
1174 FLASH_OFFSET_ERASE_REGIONS +
1177 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
1179 erase_region_count = (tmp & 0xffff) + 1;
1180 debug ("erase_region_count = %d erase_region_size = %d\n",
1181 erase_region_count, erase_region_size);
1182 for (j = 0; j < erase_region_count; j++) {
1183 info->start[sect_cnt] = sector;
1184 sector += (erase_region_size * size_ratio);
1187 * Only read protection status from supported devices (intel...)
1189 switch (info->vendor) {
1190 case CFI_CMDSET_INTEL_EXTENDED:
1191 case CFI_CMDSET_INTEL_STANDARD:
1192 info->protect[sect_cnt] =
1193 flash_isset (info, sect_cnt,
1194 FLASH_OFFSET_PROTECT,
1195 FLASH_STATUS_PROTECT);
1198 info->protect[sect_cnt] = 0; /* default: not protected */
1205 info->sector_count = sect_cnt;
1206 /* multiply the size by the number of chips */
1207 info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
1208 info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
1209 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
1210 info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
1211 tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) *
1212 (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT));
1213 info->buffer_write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */
1214 tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) *
1215 (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT));
1216 info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */
1217 info->flash_id = FLASH_MAN_CFI;
1218 if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
1219 info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
1223 flash_write_cmd (info, 0, 0, info->cmd_reset);
1224 return (info->size);
1227 /* loop through the sectors from the highest address
1228 * when the passed address is greater or equal to the sector address
1231 static flash_sect_t find_sector (flash_info_t * info, ulong addr)
1233 flash_sect_t sector;
1235 for (sector = info->sector_count - 1; sector >= 0; sector--) {
1236 if (addr >= info->start[sector])
1242 /*-----------------------------------------------------------------------
1244 static int flash_write_cfiword (flash_info_t * info, ulong dest,
1251 ctladdr.cp = flash_make_addr (info, 0, 0);
1252 cptr.cp = (uchar *) dest;
1255 /* Check if Flash is (sufficiently) erased */
1256 switch (info->portwidth) {
1257 case FLASH_CFI_8BIT:
1258 flag = ((cptr.cp[0] & cword.c) == cword.c);
1260 case FLASH_CFI_16BIT:
1261 flag = ((cptr.wp[0] & cword.w) == cword.w);
1263 case FLASH_CFI_32BIT:
1264 flag = ((cptr.lp[0] & cword.l) == cword.l);
1266 case FLASH_CFI_64BIT:
1267 flag = ((cptr.llp[0] & cword.ll) == cword.ll);
1275 /* Disable interrupts which might cause a timeout here */
1276 flag = disable_interrupts ();
1278 switch (info->vendor) {
1279 case CFI_CMDSET_INTEL_EXTENDED:
1280 case CFI_CMDSET_INTEL_STANDARD:
1281 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
1282 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
1284 case CFI_CMDSET_AMD_EXTENDED:
1285 case CFI_CMDSET_AMD_STANDARD:
1286 flash_unlock_seq (info, 0);
1287 flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
1291 switch (info->portwidth) {
1292 case FLASH_CFI_8BIT:
1293 cptr.cp[0] = cword.c;
1295 case FLASH_CFI_16BIT:
1296 cptr.wp[0] = cword.w;
1298 case FLASH_CFI_32BIT:
1299 cptr.lp[0] = cword.l;
1301 case FLASH_CFI_64BIT:
1302 cptr.llp[0] = cword.ll;
1306 /* re-enable interrupts if necessary */
1308 enable_interrupts ();
1310 return flash_full_status_check (info, find_sector (info, dest),
1311 info->write_tout, "write");
1314 #ifdef CFG_FLASH_USE_BUFFER_WRITE
1316 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
1319 flash_sect_t sector;
1322 volatile cfiptr_t src;
1323 volatile cfiptr_t dst;
1325 switch (info->vendor) {
1326 case CFI_CMDSET_INTEL_STANDARD:
1327 case CFI_CMDSET_INTEL_EXTENDED:
1329 dst.cp = (uchar *) dest;
1330 sector = find_sector (info, dest);
1331 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1332 flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
1333 if ((retcode = flash_status_check (info, sector, info->buffer_write_tout,
1334 "write to buffer")) == ERR_OK) {
1335 /* reduce the number of loops by the width of the port */
1336 switch (info->portwidth) {
1337 case FLASH_CFI_8BIT:
1340 case FLASH_CFI_16BIT:
1343 case FLASH_CFI_32BIT:
1346 case FLASH_CFI_64BIT:
1353 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
1355 switch (info->portwidth) {
1356 case FLASH_CFI_8BIT:
1357 *dst.cp++ = *src.cp++;
1359 case FLASH_CFI_16BIT:
1360 *dst.wp++ = *src.wp++;
1362 case FLASH_CFI_32BIT:
1363 *dst.lp++ = *src.lp++;
1365 case FLASH_CFI_64BIT:
1366 *dst.llp++ = *src.llp++;
1373 flash_write_cmd (info, sector, 0,
1374 FLASH_CMD_WRITE_BUFFER_CONFIRM);
1375 retcode = flash_full_status_check (info, sector,
1376 info->buffer_write_tout,
1381 case CFI_CMDSET_AMD_STANDARD:
1382 case CFI_CMDSET_AMD_EXTENDED:
1384 dst.cp = (uchar *) dest;
1385 sector = find_sector (info, dest);
1387 flash_unlock_seq(info,0);
1388 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER);
1390 switch (info->portwidth) {
1391 case FLASH_CFI_8BIT:
1393 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
1394 while (cnt-- > 0) *dst.cp++ = *src.cp++;
1396 case FLASH_CFI_16BIT:
1398 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
1399 while (cnt-- > 0) *dst.wp++ = *src.wp++;
1401 case FLASH_CFI_32BIT:
1403 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
1404 while (cnt-- > 0) *dst.lp++ = *src.lp++;
1406 case FLASH_CFI_64BIT:
1408 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
1409 while (cnt-- > 0) *dst.llp++ = *src.llp++;
1415 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
1416 retcode = flash_full_status_check (info, sector, info->buffer_write_tout,
1421 debug ("Unknown Command Set\n");
1425 #endif /* CFG_FLASH_USE_BUFFER_WRITE */
1426 #endif /* CFG_FLASH_CFI */