drivers/cache/cache-v5l2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Andes Technology Corporation
   4  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cache.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <dm/ofnode.h>
  13
  14 struct l2cache {
  15         volatile u64    configure;
  16         volatile u64    control;
  17         volatile u64    hpm0;
  18         volatile u64    hpm1;
  19         volatile u64    hpm2;
  20         volatile u64    hpm3;
  21         volatile u64    error_status;
  22         volatile u64    ecc_error;
  23         volatile u64    cctl_command0;
  24         volatile u64    cctl_access_line0;
  25         volatile u64    cctl_command1;
  26         volatile u64    cctl_access_line1;
  27         volatile u64    cctl_command2;
  28         volatile u64    cctl_access_line2;
  29         volatile u64    cctl_command3;
  30         volatile u64    cctl_access_line4;
  31         volatile u64    cctl_status;
  32 };
  33
  34 /* Control Register */
  35 #define L2_ENABLE       0x1
  36 /* prefetch */
  37 #define IPREPETCH_OFF   3
  38 #define DPREPETCH_OFF   5
  39 #define IPREPETCH_MSK   (3 << IPREPETCH_OFF)
  40 #define DPREPETCH_MSK   (3 << DPREPETCH_OFF)
  41 /* tag ram */
  42 #define TRAMOCTL_OFF    8
  43 #define TRAMICTL_OFF    10
  44 #define TRAMOCTL_MSK    (3 << TRAMOCTL_OFF)
  45 #define TRAMICTL_MSK    BIT(TRAMICTL_OFF)
  46 /* data ram */
  47 #define DRAMOCTL_OFF    11
  48 #define DRAMICTL_OFF    13
  49 #define DRAMOCTL_MSK    (3 << DRAMOCTL_OFF)
  50 #define DRAMICTL_MSK    BIT(DRAMICTL_OFF)
  51
  52 /* CCTL Command Register */
  53 #define CCTL_CMD_REG(base, hart)        ((ulong)(base) + 0x40 + (hart) * 0x10)
  54 #define L2_WBINVAL_ALL  0x12
  55
  56 /* CCTL Status Register */
  57 #define CCTL_STATUS_MSK(hart)           (0xf << ((hart) * 4))
  58 #define CCTL_STATUS_IDLE(hart)          (0 << ((hart) * 4))
  59 #define CCTL_STATUS_PROCESS(hart)       (1 << ((hart) * 4))
  60 #define CCTL_STATUS_ILLEGAL(hart)       (2 << ((hart) * 4))
  61
  62 DECLARE_GLOBAL_DATA_PTR;
  63
  64 struct v5l2_plat {
  65         struct l2cache  *regs;
  66         u32             iprefetch;
  67         u32             dprefetch;
  68         u32             tram_ctl[2];
  69         u32             dram_ctl[2];
  70 };
  71
  72 static int v5l2_enable(struct udevice *dev)
  73 {
  74         struct v5l2_plat *plat = dev_get_platdata(dev);
  75         volatile struct l2cache *regs = plat->regs;
  76
  77         if (regs)
  78                 setbits_le32(&regs->control, L2_ENABLE);
  79
  80         return 0;
  81 }
  82
  83 static int v5l2_disable(struct udevice *dev)
  84 {
  85         struct v5l2_plat *plat = dev_get_platdata(dev);
  86         volatile struct l2cache *regs = plat->regs;
  87         u8 hart = gd->arch.boot_hart;
  88         void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
  89
  90         if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
  91                 writel(L2_WBINVAL_ALL, cctlcmd);
  92
  93                 while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
  94                         if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
  95                                 printf("L2 flush illegal! hanging...");
  96                                 hang();
  97                         }
  98                 }
  99                 clrbits_le32(&regs->control, L2_ENABLE);
 100         }
 101
 102         return 0;
 103 }
 104
 105 static int v5l2_ofdata_to_platdata(struct udevice *dev)
 106 {
 107         struct v5l2_plat *plat = dev_get_platdata(dev);
 108         struct l2cache *regs;
 109
 110         regs = (struct l2cache *)dev_read_addr(dev);
 111         plat->regs = regs;
 112
 113         plat->iprefetch = -EINVAL;
 114         plat->dprefetch = -EINVAL;
 115         plat->tram_ctl[0] = -EINVAL;
 116         plat->dram_ctl[0] = -EINVAL;
 117
 118         /* Instruction and data fetch prefetch depth */
 119         dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
 120         dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
 121
 122         /* Set tag RAM and data RAM setup and output cycle */
 123         dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
 124         dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
 125
 126         return 0;
 127 }
 128
 129 static int v5l2_probe(struct udevice *dev)
 130 {
 131         struct v5l2_plat *plat = dev_get_platdata(dev);
 132         struct l2cache *regs = plat->regs;
 133         u32 ctl_val;
 134
 135         ctl_val = readl(&regs->control);
 136
 137         if (!(ctl_val & L2_ENABLE))
 138                 ctl_val |= L2_ENABLE;
 139
 140         if (plat->iprefetch != -EINVAL) {
 141                 ctl_val &= ~(IPREPETCH_MSK);
 142                 ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
 143         }
 144
 145         if (plat->dprefetch != -EINVAL) {
 146                 ctl_val &= ~(DPREPETCH_MSK);
 147                 ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
 148         }
 149
 150         if (plat->tram_ctl[0] != -EINVAL) {
 151                 ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
 152                 ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
 153                 ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
 154         }
 155
 156         if (plat->dram_ctl[0] != -EINVAL) {
 157                 ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
 158                 ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
 159                 ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
 160         }
 161
 162         writel(ctl_val, &regs->control);
 163
 164         return 0;
 165 }
 166
 167 static const struct udevice_id v5l2_cache_ids[] = {
 168         { .compatible = "v5l2cache" },
 169         {}
 170 };
 171
 172 static const struct cache_ops v5l2_cache_ops = {
 173         .enable         = v5l2_enable,
 174         .disable        = v5l2_disable,
 175 };
 176
 177 U_BOOT_DRIVER(v5l2_cache) = {
 178         .name   = "v5l2_cache",
 179         .id     = UCLASS_CACHE,
 180         .of_match = v5l2_cache_ids,
 181         .ofdata_to_platdata = v5l2_ofdata_to_platdata,
 182         .probe  = v5l2_probe,
 183         .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
 184         .ops = &v5l2_cache_ops,
 185         .flags  = DM_FLAG_PRE_RELOC,
 186 };