1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
10 #include <asm/pl310.h>
12 static void l2c310_of_parse_and_init(struct udevice *dev)
14 u32 tag[3] = { 0, 0, 0 };
15 u32 saved_reg, prefetch;
16 struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
18 /* Disable the L2 Cache */
19 clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
21 saved_reg = readl(®s->pl310_aux_ctrl);
22 if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
24 saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
26 saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
29 if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
31 saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
33 saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
36 saved_reg |= dev_read_bool(dev, "arm,shared-override");
37 writel(saved_reg, ®s->pl310_aux_ctrl);
39 saved_reg = readl(®s->pl310_tag_latency_ctrl);
40 if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
41 saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
42 L310_LATENCY_CTRL_WR(tag[1] - 1) |
43 L310_LATENCY_CTRL_SETUP(tag[2] - 1);
44 writel(saved_reg, ®s->pl310_tag_latency_ctrl);
46 saved_reg = readl(®s->pl310_data_latency_ctrl);
47 if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
48 saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
49 L310_LATENCY_CTRL_WR(tag[1] - 1) |
50 L310_LATENCY_CTRL_SETUP(tag[2] - 1);
51 writel(saved_reg, ®s->pl310_data_latency_ctrl);
53 /* Enable the L2 cache */
54 setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
57 static int l2x0_probe(struct udevice *dev)
59 l2c310_of_parse_and_init(dev);
65 static const struct udevice_id l2x0_ids[] = {
66 { .compatible = "arm,pl310-cache" },
70 U_BOOT_DRIVER(pl310_cache) = {
71 .name = "pl310_cache",
75 .flags = DM_FLAG_PRE_RELOC,