5 menu "Cache Controller drivers"
8 bool "Enable Driver Model for Cache controllers"
11 Enable driver model for cache controllers that are found on
12 most CPU's. Cache is memory that the CPU can access directly and
13 is usually located on the same chip. This uclass can be used for
14 configuring settings that be found from a device tree file.
17 tristate "PL310 cache driver"
21 This driver is for the PL310 cache controller commonly found on
22 ARMv7(32-bit) devices. The driver configures the cache settings
23 found in the device tree.
26 bool "Andes V5L2 cache driver"
28 depends on RISCV_NDS_CACHE
30 Support Andes V5L2 cache controller in AE350 platform.
31 It will configure tag and data ram timing control from the
32 device tree and enable L2 cache.
35 bool "Arteris Ncore cache coherent unit driver"
38 This driver is for the Arteris Ncore cache coherent unit (CCU)
39 controller. The driver initializes cache directories and coherent