2 * Copyright (c) 2004 Picture Elements, Inc.
3 * Stephen Williams (XXXXXXXXXXXXXXXX)
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
22 * The Xilinx SystemACE chip support is activated by defining
23 * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE
24 * to set the base address of the device. This code currently
25 * assumes that the chip is connected via a byte-wide bus.
27 * The CONFIG_SYSTEMACE also adds to fat support the device class
28 * "ace" that allows the user to execute "fatls ace 0" and the
29 * like. This works by making the systemace_get_dev function
30 * available to cmd_fat.c:get_dev and filling in a block device
31 * description that has all the bits needed for FAT support to
34 * According to Xilinx technical support, before accessing the
35 * SystemACE CF you need to set the following control bits:
43 #include <systemace.h>
48 * The ace_readw and writew functions read/write 16bit words, but the
49 * offset value is the BYTE offset as most used in the Xilinx
50 * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined
51 * to be the base address for the chip, usually in the local
55 static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
56 static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
58 static void ace_writew(u16 val, unsigned off)
61 #if !defined(__BIG_ENDIAN)
62 writeb(val >> 8, base + off);
63 writeb(val, base + off + 1);
65 writeb(val, base + off);
66 writeb(val >> 8, base + off + 1);
69 out16(base + off, val);
72 static u16 ace_readw(unsigned off)
75 #if !defined(__BIG_ENDIAN)
76 return (readb(base + off) << 8) | readb(base + off + 1);
78 return readb(base + off) | (readb(base + off + 1) << 8);
82 return in16(base + off);
85 static unsigned long systemace_read(int dev, unsigned long start,
86 lbaint_t blkcnt, void *buffer);
88 static block_dev_desc_t systemace_dev = { 0 };
90 static int get_cf_lock(void)
94 /* CONTROLREG = LOCKREG */
95 unsigned val = ace_readw(0x18);
97 ace_writew((val & 0xffff), 0x18);
99 /* Wait for MPULOCK in STATUSREG[15:0] */
100 while (!(ace_readw(0x04) & 0x0002)) {
112 static void release_cf_lock(void)
114 unsigned val = ace_readw(0x18);
116 ace_writew((val & 0xffff), 0x18);
119 #ifdef CONFIG_PARTITIONS
120 block_dev_desc_t *systemace_get_dev(int dev)
122 /* The first time through this, the systemace_dev object is
123 not yet initialized. In that case, fill it in. */
124 if (systemace_dev.blksz == 0) {
125 systemace_dev.if_type = IF_TYPE_UNKNOWN;
126 systemace_dev.dev = 0;
127 systemace_dev.part_type = PART_TYPE_UNKNOWN;
128 systemace_dev.type = DEV_TYPE_HARDDISK;
129 systemace_dev.blksz = 512;
130 systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
131 systemace_dev.removable = 1;
132 systemace_dev.block_read = systemace_read;
135 * Ensure the correct bus mode (8/16 bits) gets enabled
137 ace_writew(width == 8 ? 0 : 0x0001, 0);
139 init_part(&systemace_dev);
143 return &systemace_dev;
148 * This function is called (by dereferencing the block_read pointer in
149 * the dev_desc) to read blocks of data. The return value is the
150 * number of blocks read. A zero return indicates an error.
152 static unsigned long systemace_read(int dev, unsigned long start,
153 lbaint_t blkcnt, void *buffer)
156 unsigned blk_countdown;
157 unsigned char *dp = buffer;
160 if (get_cf_lock() < 0) {
161 unsigned status = ace_readw(0x04);
163 /* If CFDETECT is false, card is missing. */
164 if (!(status & 0x0010)) {
165 printf("** CompactFlash card not present. **\n");
169 printf("**** ACE locked away from me (STATUSREG=%04x)\n",
173 #ifdef DEBUG_SYSTEMACE
174 printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
179 val = ace_readw(0x04);
181 /* If CFDETECT is false, card is missing. */
182 if (!(val & 0x0010)) {
183 printf("**** ACE CompactFlash not found.\n");
188 /* If RDYFORCMD, then we are ready to go. */
193 printf("**** SystemACE not ready.\n");
202 /* The SystemACE can only transfer 256 sectors at a time, so
203 limit the current chunk of sectors. The blk_countdown
204 variable is the number of sectors left to transfer. */
206 blk_countdown = blkcnt;
207 while (blk_countdown > 0) {
208 unsigned trans = blk_countdown;
213 #ifdef DEBUG_SYSTEMACE
214 printf("... transfer %lu sector in a chunk\n", trans);
216 /* Write LBA block address */
217 ace_writew((start >> 0) & 0xffff, 0x10);
218 ace_writew((start >> 16) & 0x0fff, 0x12);
220 /* NOTE: in the Write Sector count below, a count of 0
221 causes a transfer of 256, so &0xff gives the right
222 value for whatever transfer count we want. */
224 /* Write sector count | ReadMemCardData. */
225 ace_writew((trans & 0xff) | 0x0300, 0x14);
228 * For FPGA configuration via SystemACE is reset unacceptable
229 * CFGDONE bit in STATUSREG is not set to 1.
231 #ifndef SYSTEMACE_CONFIG_FPGA
232 /* Reset the configruation controller */
233 val = ace_readw(0x18);
235 ace_writew(val, 0x18);
242 /* Wait for buffer to become ready. */
243 while (!(ace_readw(0x04) & 0x0020)) {
247 /* Read 16 words of 2bytes from the sector buffer. */
248 for (idx = 0; idx < 16; idx += 1) {
249 unsigned short val = ace_readw(0x40);
251 *dp++ = (val >> 8) & 0xff;
257 /* Clear the configruation controller reset */
258 val = ace_readw(0x18);
260 ace_writew(val, 0x18);
262 /* Count the blocks we transfer this time. */
264 blk_countdown -= trans;