2 * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <asm/fsl_serdes.h>
32 #ifndef CONFIG_SYS_SATA1_FLAGS
33 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
35 #ifndef CONFIG_SYS_SATA2_FLAGS
36 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
39 static struct fsl_sata_info fsl_sata_info[] = {
41 {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
46 {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
52 static inline void sdelay(unsigned long sec)
55 for (i = 0; i < sec; i++)
59 static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
61 printf("Status FIS dump:\n\r");
62 printf("fis_type: %02x\n\r", s->fis_type);
63 printf("pm_port_i: %02x\n\r", s->pm_port_i);
64 printf("status: %02x\n\r", s->status);
65 printf("error: %02x\n\r", s->error);
66 printf("lba_low: %02x\n\r", s->lba_low);
67 printf("lba_mid: %02x\n\r", s->lba_mid);
68 printf("lba_high: %02x\n\r", s->lba_high);
69 printf("device: %02x\n\r", s->device);
70 printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
71 printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
72 printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
73 printf("res1: %02x\n\r", s->res1);
74 printf("sector_count: %02x\n\r", s->sector_count);
75 printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
78 static int ata_wait_register(unsigned __iomem *addr, u32 mask,
79 u32 val, u32 timeout_msec)
84 for (i = 0; (((temp = in_le32(addr)) & mask) != val)
85 && i < timeout_msec; i++)
87 return (i < timeout_msec) ? 0 : -1;
90 int init_sata(int dev)
93 cmd_hdr_tbl_t *cmd_hdr;
96 fsl_sata_reg_t __iomem *reg;
101 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
102 printf("the sata index %d is out of ranges\n\r", dev);
106 #ifdef CONFIG_MPC85xx
107 if ((dev == 0) && (!is_serdes_configured(SATA1))) {
108 printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
111 if ((dev == 1) && (!is_serdes_configured(SATA2))) {
112 printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
117 /* Allocate SATA device driver struct */
118 sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
120 printf("alloc the sata device struct failed\n\r");
123 /* Zero all of the device driver struct */
124 memset((void *)sata, 0, sizeof(fsl_sata_t));
126 /* Save the private struct to block device struct */
127 sata_dev_desc[dev].priv = (void *)sata;
129 sprintf(sata->name, "SATA%d", dev);
131 /* Set the controller register base address to device struct */
132 reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
133 sata->reg_base = reg;
135 /* Allocate the command header table, 4 bytes aligned */
136 length = sizeof(struct cmd_hdr_tbl);
137 align = SATA_HC_CMD_HDR_TBL_ALIGN;
138 sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
140 printf("alloc the command header failed\n\r");
144 cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
146 sata->cmd_hdr = cmd_hdr;
148 /* Zero all of the command header table */
149 memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
151 /* Allocate command descriptor for all command */
152 length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
153 align = SATA_HC_CMD_DESC_ALIGN;
154 sata->cmd_desc_offset = (void *)malloc(length + align);
155 if (!sata->cmd_desc_offset) {
156 printf("alloc the command descriptor failed\n\r");
159 sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
161 /* Zero all of command descriptor */
162 memset((void *)sata->cmd_desc_offset, 0, length + align);
164 /* Link the command descriptor to command header */
165 for (i = 0; i < SATA_HC_MAX_CMD; i++) {
166 cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
167 & ~(CMD_HDR_CDA_ALIGN - 1);
168 cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
171 /* To have safe state, force the controller offline */
172 val32 = in_le32(®->hcontrol);
173 val32 &= ~HCONTROL_ONOFF;
174 val32 |= HCONTROL_FORCE_OFFLINE;
175 out_le32(®->hcontrol, val32);
177 /* Wait the controller offline */
178 ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
180 /* Set the command header base address to CHBA register to tell DMA */
181 out_le32(®->chba, (u32)cmd_hdr & ~0x3);
183 /* Snoop for the command header */
184 val32 = in_le32(®->hcontrol);
185 val32 |= HCONTROL_HDR_SNOOP;
186 out_le32(®->hcontrol, val32);
188 /* Disable all of interrupts */
189 val32 = in_le32(®->hcontrol);
190 val32 &= ~HCONTROL_INT_EN_ALL;
191 out_le32(®->hcontrol, val32);
193 /* Clear all of interrupts */
194 val32 = in_le32(®->hstatus);
195 out_le32(®->hstatus, val32);
197 /* Set the ICC, no interrupt coalescing */
198 out_le32(®->icc, 0x01000000);
200 /* No PM attatched, the SATA device direct connect */
201 out_le32(®->cqpmp, 0);
203 /* Clear SError register */
204 val32 = in_le32(®->serror);
205 out_le32(®->serror, val32);
207 /* Clear CER register */
208 val32 = in_le32(®->cer);
209 out_le32(®->cer, val32);
211 /* Clear DER register */
212 val32 = in_le32(®->der);
213 out_le32(®->der, val32);
215 /* No device detection or initialization action requested */
216 out_le32(®->scontrol, 0x00000300);
218 /* Configure the transport layer, default value */
219 out_le32(®->transcfg, 0x08000016);
221 /* Configure the link layer, default value */
222 out_le32(®->linkcfg, 0x0000ff34);
224 /* Bring the controller online */
225 val32 = in_le32(®->hcontrol);
226 val32 |= HCONTROL_ONOFF;
227 out_le32(®->hcontrol, val32);
231 /* print sata device name */
233 printf("%s ", sata->name);
235 printf(" %s ", sata->name);
237 /* Wait PHY RDY signal changed for 500ms */
238 ata_wait_register(®->hstatus, HSTATUS_PHY_RDY,
239 HSTATUS_PHY_RDY, 500);
242 val32 = in_le32(®->hstatus);
243 if (val32 & HSTATUS_PHY_RDY) {
247 printf("(No RDY)\n\r");
251 /* Wait for signature updated, which is 1st D2H */
252 ata_wait_register(®->hstatus, HSTATUS_SIGNATURE,
253 HSTATUS_SIGNATURE, 10000);
255 if (val32 & HSTATUS_SIGNATURE) {
256 sig = in_le32(®->sig);
257 debug("Signature updated, the sig =%08x\n\r", sig);
258 sata->ata_device_type = ata_dev_classify(sig);
261 /* Check the speed */
262 val32 = in_le32(®->sstatus);
263 if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
264 printf("(1.5 Gbps)\n\r");
265 else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
266 printf("(3 Gbps)\n\r");
271 static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
273 printf("\n\rSATA: %08x\n\r", (u32)reg);
274 printf("CQR: %08x\n\r", in_le32(®->cqr));
275 printf("CAR: %08x\n\r", in_le32(®->car));
276 printf("CCR: %08x\n\r", in_le32(®->ccr));
277 printf("CER: %08x\n\r", in_le32(®->cer));
278 printf("CQR: %08x\n\r", in_le32(®->cqr));
279 printf("DER: %08x\n\r", in_le32(®->der));
280 printf("CHBA: %08x\n\r", in_le32(®->chba));
281 printf("HStatus: %08x\n\r", in_le32(®->hstatus));
282 printf("HControl: %08x\n\r", in_le32(®->hcontrol));
283 printf("CQPMP: %08x\n\r", in_le32(®->cqpmp));
284 printf("SIG: %08x\n\r", in_le32(®->sig));
285 printf("ICC: %08x\n\r", in_le32(®->icc));
286 printf("SStatus: %08x\n\r", in_le32(®->sstatus));
287 printf("SError: %08x\n\r", in_le32(®->serror));
288 printf("SControl: %08x\n\r", in_le32(®->scontrol));
289 printf("SNotification: %08x\n\r", in_le32(®->snotification));
290 printf("TransCfg: %08x\n\r", in_le32(®->transcfg));
291 printf("TransStatus: %08x\n\r", in_le32(®->transstatus));
292 printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg));
293 printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1));
294 printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2));
295 printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus));
296 printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1));
297 printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg));
298 printf("SYSPR: %08x\n\r", in_be32(®->syspr));
301 static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
302 int is_ncq, int tag, u8 *buffer, u32 len)
304 cmd_hdr_entry_t *cmd_hdr;
305 cmd_desc_t *cmd_desc;
312 fsl_sata_reg_t __iomem *reg = sata->reg_base;
315 /* Check xfer length */
316 if (len > SATA_HC_MAX_XFER_LEN) {
317 printf("max transfer length is 64MB\n\r");
321 /* Setup the command descriptor */
322 cmd_desc = sata->cmd_desc + tag;
324 /* Get the pointer cfis of command descriptor */
325 h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
327 /* Zero the cfis of command descriptor */
328 memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
330 /* Copy the cfis from user to command descriptor */
331 h2d->fis_type = cfis->fis_type;
332 h2d->pm_port_c = cfis->pm_port_c;
333 h2d->command = cfis->command;
335 h2d->features = cfis->features;
336 h2d->features_exp = cfis->features_exp;
338 h2d->lba_low = cfis->lba_low;
339 h2d->lba_mid = cfis->lba_mid;
340 h2d->lba_high = cfis->lba_high;
341 h2d->lba_low_exp = cfis->lba_low_exp;
342 h2d->lba_mid_exp = cfis->lba_mid_exp;
343 h2d->lba_high_exp = cfis->lba_high_exp;
346 h2d->sector_count = cfis->sector_count;
347 h2d->sector_count_exp = cfis->sector_count_exp;
349 h2d->sector_count = (u8)(tag << 3);
352 h2d->device = cfis->device;
353 h2d->control = cfis->control;
355 /* Setup the PRD table */
356 prde = (prd_entry_t *)cmd_desc->prdt;
357 memset((void *)prde, 0, sizeof(struct prdt));
361 for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
364 prde->dba = cpu_to_le32((u32)buffer & ~0x3);
365 debug("dba = %08x\n\r", (u32)buffer);
367 if (len < PRD_ENTRY_MAX_XFER_SZ) {
368 ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
369 debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
370 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
375 ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
376 debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
377 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
378 buffer += PRD_ENTRY_MAX_XFER_SZ;
379 len -= PRD_ENTRY_MAX_XFER_SZ;
385 /* Setup the command slot of cmd hdr */
386 cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
388 cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
390 val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
391 val32 |= sizeof(sata_fis_h2d_t);
392 cmd_hdr->prde_fis_len = cpu_to_le32(val32);
394 cmd_hdr->ttl = cpu_to_le32(ttl);
397 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
399 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
402 tag &= CMD_HDR_ATTR_TAG;
405 debug("attribute = %08x\n\r", val32);
406 cmd_hdr->attribute = cpu_to_le32(val32);
408 /* Make sure cmd desc and cmd slot valid before commmand issue */
412 val32 = (u32)(h2d->pm_port_c & 0x0f);
413 out_le32(®->cqpmp, val32);
416 if (ata_wait_register(®->car, (1 << tag), 0, 10000))
417 printf("Wait no active time out\n\r");
420 if (!(in_le32(®->cqr) & (1 << tag))) {
422 out_le32(®->cqr, val32);
425 /* Wait command completed for 10s */
426 if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) {
428 printf("Non-NCQ command time out\n\r");
430 printf("NCQ command time out\n\r");
433 val32 = in_le32(®->cer);
437 fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
438 printf("CE at device\n\r");
439 fsl_sata_dump_regs(reg);
440 der = in_le32(®->der);
441 out_le32(®->cer, val32);
442 out_le32(®->der, der);
445 /* Clear complete flags */
446 val32 = in_le32(®->ccr);
447 out_le32(®->ccr, val32);
452 static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
453 int tag, u8 *buffer, u32 len)
458 static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
459 enum cmd_type command_type, int tag, u8 *buffer, u32 len)
463 if (tag > SATA_HC_MAX_CMD || tag < 0) {
464 printf("tag is out of range, tag=%d\n\r", tag);
468 switch (command_type) {
470 rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
473 rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
476 rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
479 case CMD_VENDOR_BIST:
481 printf("not support now\n\r");
490 static void fsl_sata_identify(int dev, u16 *id)
492 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
493 struct sata_fis_h2d h2d, *cfis = &h2d;
495 memset(cfis, 0, sizeof(struct sata_fis_h2d));
497 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
498 cfis->pm_port_c = 0x80; /* is command */
499 cfis->command = ATA_CMD_ID_ATA;
501 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
502 ata_swap_buf_le16(id, ATA_ID_WORDS);
505 static void fsl_sata_xfer_mode(int dev, u16 *id)
507 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
509 sata->pio = id[ATA_ID_PIO_MODES];
510 sata->mwdma = id[ATA_ID_MWDMA_MODES];
511 sata->udma = id[ATA_ID_UDMA_MODES];
512 debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
515 static void fsl_sata_set_features(int dev)
517 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
518 struct sata_fis_h2d h2d, *cfis = &h2d;
521 memset(cfis, 0, sizeof(struct sata_fis_h2d));
523 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
524 cfis->pm_port_c = 0x80; /* is command */
525 cfis->command = ATA_CMD_SET_FEATURES;
526 cfis->features = SETFEATURES_XFER;
528 /* First check the device capablity */
529 udma_cap = (u8)(sata->udma & 0xff);
530 debug("udma_cap %02x\n\r", udma_cap);
532 if (udma_cap == ATA_UDMA6)
533 cfis->sector_count = XFER_UDMA_6;
534 if (udma_cap == ATA_UDMA5)
535 cfis->sector_count = XFER_UDMA_5;
536 if (udma_cap == ATA_UDMA4)
537 cfis->sector_count = XFER_UDMA_4;
538 if (udma_cap == ATA_UDMA3)
539 cfis->sector_count = XFER_UDMA_3;
541 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
544 static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
546 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
547 struct sata_fis_h2d h2d, *cfis = &h2d;
552 memset(cfis, 0, sizeof(struct sata_fis_h2d));
554 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
555 cfis->pm_port_c = 0x80; /* is command */
556 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
557 cfis->device = ATA_LBA;
559 cfis->device |= (block >> 24) & 0xf;
560 cfis->lba_high = (block >> 16) & 0xff;
561 cfis->lba_mid = (block >> 8) & 0xff;
562 cfis->lba_low = block & 0xff;
563 cfis->sector_count = (u8)(blkcnt & 0xff);
565 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
569 static void fsl_sata_flush_cache(int dev)
571 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
572 struct sata_fis_h2d h2d, *cfis = &h2d;
574 memset(cfis, 0, sizeof(struct sata_fis_h2d));
576 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
577 cfis->pm_port_c = 0x80; /* is command */
578 cfis->command = ATA_CMD_FLUSH;
580 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
583 static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
585 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
586 struct sata_fis_h2d h2d, *cfis = &h2d;
591 memset(cfis, 0, sizeof(struct sata_fis_h2d));
593 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
594 cfis->pm_port_c = 0x80; /* is command */
596 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
599 cfis->lba_high_exp = (block >> 40) & 0xff;
600 cfis->lba_mid_exp = (block >> 32) & 0xff;
601 cfis->lba_low_exp = (block >> 24) & 0xff;
602 cfis->lba_high = (block >> 16) & 0xff;
603 cfis->lba_mid = (block >> 8) & 0xff;
604 cfis->lba_low = block & 0xff;
605 cfis->device = ATA_LBA;
606 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
607 cfis->sector_count = blkcnt & 0xff;
609 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
613 static u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer,
616 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
617 struct sata_fis_h2d h2d, *cfis = &h2d;
621 if (sata->lba48 != 1) {
622 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
628 memset(cfis, 0, sizeof(struct sata_fis_h2d));
630 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
631 cfis->pm_port_c = 0x80; /* is command */
633 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
634 : ATA_CMD_FPDMA_READ;
636 cfis->lba_high_exp = (block >> 40) & 0xff;
637 cfis->lba_mid_exp = (block >> 32) & 0xff;
638 cfis->lba_low_exp = (block >> 24) & 0xff;
639 cfis->lba_high = (block >> 16) & 0xff;
640 cfis->lba_mid = (block >> 8) & 0xff;
641 cfis->lba_low = block & 0xff;
643 cfis->device = ATA_LBA;
644 cfis->features_exp = (blkcnt >> 8) & 0xff;
645 cfis->features = blkcnt & 0xff;
647 if (sata->queue_depth >= SATA_HC_MAX_CMD)
648 ncq_channel = SATA_HC_MAX_CMD - 1;
650 ncq_channel = sata->queue_depth - 1;
652 /* Use the latest queue */
653 fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
657 static void fsl_sata_flush_cache_ext(int dev)
659 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
660 struct sata_fis_h2d h2d, *cfis = &h2d;
662 memset(cfis, 0, sizeof(struct sata_fis_h2d));
664 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
665 cfis->pm_port_c = 0x80; /* is command */
666 cfis->command = ATA_CMD_FLUSH_EXT;
668 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
671 static void fsl_sata_init_wcache(int dev, u16 *id)
673 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
675 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
677 if (ata_id_has_flush(id))
679 if (ata_id_has_flush_ext(id))
683 static int fsl_sata_get_wcache(int dev)
685 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
689 static int fsl_sata_get_flush(int dev)
691 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
695 static int fsl_sata_get_flush_ext(int dev)
697 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
698 return sata->flush_ext;
701 static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
702 const void *buffer, int is_write)
712 max_blks = ATA_MAX_SECTORS_LBA48;
714 if (blks > max_blks) {
715 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
716 fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
718 fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
721 addr += ATA_SECT_SIZE * max_blks;
723 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
724 fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
726 fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
729 addr += ATA_SECT_SIZE * blks;
736 static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt,
737 const void *buffer, int is_write)
747 max_blks = ATA_MAX_SECTORS;
749 if (blks > max_blks) {
750 fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
753 addr += ATA_SECT_SIZE * max_blks;
755 fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
758 addr += ATA_SECT_SIZE * blks;
766 * SATA interface between low level driver and command layer
768 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
771 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
774 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
776 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
780 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
783 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
786 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
787 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
788 fsl_sata_flush_cache_ext(dev);
790 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
791 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
792 fsl_sata_flush_cache(dev);
797 int scan_sata(int dev)
799 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
800 unsigned char serial[ATA_ID_SERNO_LEN + 1];
801 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
802 unsigned char product[ATA_ID_PROD_LEN + 1];
806 /* if no detected link */
810 id = (u16 *)malloc(ATA_ID_WORDS * 2);
812 printf("id malloc failed\n\r");
816 /* Identify device to get information */
817 fsl_sata_identify(dev, id);
820 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
821 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
823 /* Firmware version */
824 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
825 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
828 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
829 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
832 n_sectors = ata_id_n_sectors(id);
833 sata_dev_desc[dev].lba = (u32)n_sectors;
836 /* Check if support LBA48 */
837 if (ata_id_has_lba48(id)) {
839 debug("Device support LBA48\n\r");
841 debug("Device supports LBA28\n\r");
844 /* Get the NCQ queue depth from device */
845 sata->queue_depth = ata_id_queue_depth(id);
847 /* Get the xfer mode from device */
848 fsl_sata_xfer_mode(dev, id);
850 /* Get the write cache status from device */
851 fsl_sata_init_wcache(dev, id);
853 /* Set the xfer mode to highest speed */
854 fsl_sata_set_features(dev);
856 fsl_sata_identify(dev, id);