2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <linux/ctype.h>
16 #include <asm/errno.h>
18 #include <linux/bitops.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include "dwc_ahsata.h"
23 struct sata_port_regs {
47 struct sata_host_regs {
76 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
77 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
79 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
83 static inline u32 ahci_port_base(u32 base, u32 port)
85 return base + 0x100 + (port * 0x80);
88 static int waiting_for_cmd_completed(u8 *offset,
96 ((status = readl(offset)) & sign) && i < timeout_msec;
100 return (i < timeout_msec) ? 0 : -1;
103 static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
106 struct sata_host_regs *host_mmio =
107 (struct sata_host_regs *)probe_ent->mmio_base;
109 writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
110 writel(0x02060b14, &(host_mmio->oobr));
115 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
117 u32 tmp, cap_save, num_ports;
118 int i, j, timeout = 1000;
119 struct sata_port_regs *port_mmio = NULL;
120 struct sata_host_regs *host_mmio =
121 (struct sata_host_regs *)probe_ent->mmio_base;
122 int clk = mxc_get_clock(MXC_SATA_CLK);
124 cap_save = readl(&(host_mmio->cap));
125 cap_save |= SATA_HOST_CAP_SSS;
127 /* global controller reset */
128 tmp = readl(&(host_mmio->ghc));
129 if ((tmp & SATA_HOST_GHC_HR) == 0)
130 writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
132 while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
137 debug("controller reset failed (0x%x)\n", tmp);
142 writel(clk / 1000, &(host_mmio->timer1ms));
144 ahci_setup_oobr(probe_ent, 0);
146 writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
147 writel(cap_save, &(host_mmio->cap));
148 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
149 writel_with_flush((1 << num_ports) - 1,
153 * Determine which Ports are implemented by the DWC_ahsata,
154 * by reading the PI register. This bit map value aids the
155 * software to determine how many Ports are available and
156 * which Port registers need to be initialized.
158 probe_ent->cap = readl(&(host_mmio->cap));
159 probe_ent->port_map = readl(&(host_mmio->pi));
161 /* Determine how many command slots the HBA supports */
163 (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1;
165 debug("cap 0x%x port_map 0x%x n_ports %d\n",
166 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
168 for (i = 0; i < probe_ent->n_ports; i++) {
169 probe_ent->port[i].port_mmio =
170 ahci_port_base((u32)host_mmio, i);
172 (struct sata_port_regs *)probe_ent->port[i].port_mmio;
174 /* Ensure that the DWC_ahsata is in idle state */
175 tmp = readl(&(port_mmio->cmd));
178 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
179 * are all cleared, the Port is in an idle state.
181 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
182 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
185 * System software places a Port into the idle state by
186 * clearing P#CMD.ST and waiting for P#CMD.CR to return
189 tmp &= ~SATA_PORT_CMD_ST;
190 writel_with_flush(tmp, &(port_mmio->cmd));
193 * spec says 500 msecs for each bit, so
194 * this is slightly incorrect.
199 while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
204 debug("port reset failed (0x%x)\n", tmp);
210 tmp = readl(&(port_mmio->cmd));
211 writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
213 /* Wait for spin-up to finish */
215 while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
219 debug("Spin-Up can't finish!\n");
223 for (j = 0; j < 100; ++j) {
225 tmp = readl(&(port_mmio->ssts));
226 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
227 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
231 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
233 while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
237 debug("Can't find DIAG_X set!\n");
242 * For each implemented Port, clear the P#SERR
243 * register, by writing ones to each implemented\
246 tmp = readl(&(port_mmio->serr));
247 debug("P#SERR 0x%x\n",
249 writel(tmp, &(port_mmio->serr));
251 /* Ack any pending irq events for this port */
252 tmp = readl(&(host_mmio->is));
253 debug("IS 0x%x\n", tmp);
255 writel(tmp, &(host_mmio->is));
257 writel(1 << i, &(host_mmio->is));
259 /* set irq mask (enables interrupts) */
260 writel(DEF_PORT_IRQ, &(port_mmio->ie));
262 /* register linkup ports */
263 tmp = readl(&(port_mmio->ssts));
264 debug("Port %d status: 0x%x\n", i, tmp);
265 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
266 probe_ent->link_port_map |= (0x01 << i);
269 tmp = readl(&(host_mmio->ghc));
270 debug("GHC 0x%x\n", tmp);
271 writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
272 tmp = readl(&(host_mmio->ghc));
273 debug("GHC 0x%x\n", tmp);
278 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
280 struct sata_host_regs *host_mmio =
281 (struct sata_host_regs *)probe_ent->mmio_base;
282 u32 vers, cap, impl, speed;
286 vers = readl(&(host_mmio->vs));
287 cap = probe_ent->cap;
288 impl = probe_ent->port_map;
290 speed = (cap & SATA_HOST_CAP_ISS_MASK)
291 >> SATA_HOST_CAP_ISS_OFFSET;
301 printf("AHCI %02x%02x.%02x%02x "
302 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
307 ((cap >> 8) & 0x1f) + 1,
316 cap & (1 << 31) ? "64bit " : "",
317 cap & (1 << 30) ? "ncq " : "",
318 cap & (1 << 28) ? "ilck " : "",
319 cap & (1 << 27) ? "stag " : "",
320 cap & (1 << 26) ? "pm " : "",
321 cap & (1 << 25) ? "led " : "",
322 cap & (1 << 24) ? "clo " : "",
323 cap & (1 << 19) ? "nz " : "",
324 cap & (1 << 18) ? "only " : "",
325 cap & (1 << 17) ? "pmp " : "",
326 cap & (1 << 15) ? "pio " : "",
327 cap & (1 << 14) ? "slum " : "",
328 cap & (1 << 13) ? "part " : "");
331 static int ahci_init_one(int pdev)
334 struct ahci_probe_ent *probe_ent = NULL;
336 probe_ent = malloc(sizeof(struct ahci_probe_ent));
337 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
338 probe_ent->dev = pdev;
340 probe_ent->host_flags = ATA_FLAG_SATA
346 probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
348 /* initialize adapter */
349 rc = ahci_host_init(probe_ent);
353 ahci_print_info(probe_ent);
355 /* Save the private struct to block device struct */
356 sata_dev_desc[pdev].priv = (void *)probe_ent;
364 static int ahci_fill_sg(struct ahci_probe_ent *probe_ent,
365 u8 port, unsigned char *buf, int buf_len)
367 struct ahci_ioports *pp = &(probe_ent->port[port]);
368 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
369 u32 sg_count, max_bytes;
372 max_bytes = MAX_DATA_BYTES_PER_SG;
373 sg_count = ((buf_len - 1) / max_bytes) + 1;
374 if (sg_count > AHCI_MAX_SG) {
375 printf("Error:Too much sg!\n");
379 for (i = 0; i < sg_count; i++) {
381 cpu_to_le32((u32)buf + i * max_bytes);
382 ahci_sg->addr_hi = 0;
383 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
388 buf_len -= max_bytes;
394 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
396 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
397 AHCI_CMD_SLOT_SZ * cmd_slot);
399 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
400 cmd_hdr->opts = cpu_to_le32(opts);
402 cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
403 cmd_hdr->tbl_addr_hi = 0;
406 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
408 static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
409 u8 port, struct sata_fis_h2d *cfis,
410 u8 *buf, u32 buf_len, s32 is_write)
412 struct ahci_ioports *pp = &(probe_ent->port[port]);
413 struct sata_port_regs *port_mmio =
414 (struct sata_port_regs *)pp->port_mmio;
416 int sg_count = 0, cmd_slot = 0;
418 cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
419 if (32 == cmd_slot) {
420 printf("Can't find empty command slot!\n");
424 /* Check xfer length */
425 if (buf_len > MAX_BYTES_PER_TRANS) {
426 printf("Max transfer length is %dB\n\r",
427 MAX_BYTES_PER_TRANS);
431 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
433 sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
434 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
437 flush_cache((ulong)buf, buf_len);
439 ahci_fill_cmd_slot(pp, cmd_slot, opts);
441 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
442 writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
444 if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
445 10000, 0x1 << cmd_slot)) {
446 printf("timeout exit!\n");
449 invalidate_dcache_range((int)(pp->cmd_slot),
450 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
451 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
452 pp->cmd_slot->status);
454 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
459 static void ahci_set_feature(u8 dev, u8 port)
461 struct ahci_probe_ent *probe_ent =
462 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
463 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
464 struct sata_fis_h2d *cfis = &h2d;
466 memset(cfis, 0, sizeof(struct sata_fis_h2d));
467 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
468 cfis->pm_port_c = 1 << 7;
469 cfis->command = ATA_CMD_SET_FEATURES;
470 cfis->features = SETFEATURES_XFER;
471 cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e;
473 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD);
476 static int ahci_port_start(struct ahci_probe_ent *probe_ent,
479 struct ahci_ioports *pp = &(probe_ent->port[port]);
480 struct sata_port_regs *port_mmio =
481 (struct sata_port_regs *)pp->port_mmio;
484 int timeout = 10000000;
486 debug("Enter start port: %d\n", port);
487 port_status = readl(&(port_mmio->ssts));
488 debug("Port %d status: %x\n", port, port_status);
489 if ((port_status & 0xf) != 0x03) {
490 printf("No Link on this port!\n");
494 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
497 printf("No mem for table!\n");
501 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
502 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
505 * First item in chunk of DMA memory: 32-slot command table,
506 * 32 bytes each in size
508 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
509 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
510 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
513 * Second item: Received-FIS area, 256-Byte aligned
516 mem += AHCI_RX_FIS_SZ;
519 * Third item: data area for storing a single command
520 * and its scatter-gather table
523 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
525 mem += AHCI_CMD_TBL_HDR;
527 writel_with_flush(0x00004444, &(port_mmio->dmacr));
528 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
529 writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
530 writel_with_flush(pp->rx_fis, &(port_mmio->fb));
533 writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
536 /* Wait device ready */
537 while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
538 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
542 debug("Device not ready for BSY, DRQ and"
547 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
548 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
549 PORT_CMD_START, &(port_mmio->cmd));
551 debug("Exit start port %d\n", port);
556 int init_sata(int dev)
560 struct ahci_probe_ent *probe_ent = NULL;
562 #if defined(CONFIG_MX6)
563 if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
566 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
567 printf("The sata index %d is out of ranges\n\r", dev);
573 probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
574 linkmap = probe_ent->link_port_map;
577 printf("No port device detected!\n");
581 for (i = 0; i < probe_ent->n_ports; i++) {
582 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
583 if (ahci_port_start(probe_ent, (u8)i)) {
584 printf("Can not start port %d\n", i);
587 probe_ent->hard_port_no = i;
595 int reset_sata(int dev)
597 struct ahci_probe_ent *probe_ent =
598 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
599 struct sata_host_regs *host_mmio =
600 (struct sata_host_regs *)probe_ent->mmio_base;
602 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
603 printf("The sata index %d is out of ranges\n\r", dev);
607 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
608 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
611 disable_sata_clock();
616 static void dwc_ahsata_print_info(int dev)
618 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
620 printf("SATA Device Info:\n\r");
621 #ifdef CONFIG_SYS_64BIT_LBA
622 printf("S/N: %s\n\rProduct model number: %s\n\r"
623 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
624 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
626 printf("S/N: %s\n\rProduct model number: %s\n\r"
627 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
628 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
632 static void dwc_ahsata_identify(int dev, u16 *id)
634 struct ahci_probe_ent *probe_ent =
635 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
636 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
637 struct sata_fis_h2d *cfis = &h2d;
638 u8 port = probe_ent->hard_port_no;
640 memset(cfis, 0, sizeof(struct sata_fis_h2d));
642 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
643 cfis->pm_port_c = 0x80; /* is command */
644 cfis->command = ATA_CMD_ID_ATA;
646 ahci_exec_ata_cmd(probe_ent, port, cfis,
647 (u8 *)id, ATA_ID_WORDS * 2, READ_CMD);
648 ata_swap_buf_le16(id, ATA_ID_WORDS);
651 static void dwc_ahsata_xfer_mode(int dev, u16 *id)
653 struct ahci_probe_ent *probe_ent =
654 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
656 probe_ent->pio_mask = id[ATA_ID_PIO_MODES];
657 probe_ent->udma_mask = id[ATA_ID_UDMA_MODES];
658 debug("pio %04x, udma %04x\n\r",
659 probe_ent->pio_mask, probe_ent->udma_mask);
662 static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
663 u8 *buffer, int is_write)
665 struct ahci_probe_ent *probe_ent =
666 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
667 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
668 struct sata_fis_h2d *cfis = &h2d;
669 u8 port = probe_ent->hard_port_no;
674 memset(cfis, 0, sizeof(struct sata_fis_h2d));
676 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
677 cfis->pm_port_c = 0x80; /* is command */
678 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
679 cfis->device = ATA_LBA;
681 cfis->device |= (block >> 24) & 0xf;
682 cfis->lba_high = (block >> 16) & 0xff;
683 cfis->lba_mid = (block >> 8) & 0xff;
684 cfis->lba_low = block & 0xff;
685 cfis->sector_count = (u8)(blkcnt & 0xff);
687 if (ahci_exec_ata_cmd(probe_ent, port, cfis,
688 buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0)
694 void dwc_ahsata_flush_cache(int dev)
696 struct ahci_probe_ent *probe_ent =
697 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
698 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
699 struct sata_fis_h2d *cfis = &h2d;
700 u8 port = probe_ent->hard_port_no;
702 memset(cfis, 0, sizeof(struct sata_fis_h2d));
704 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
705 cfis->pm_port_c = 0x80; /* is command */
706 cfis->command = ATA_CMD_FLUSH;
708 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
711 static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
712 u8 *buffer, int is_write)
714 struct ahci_probe_ent *probe_ent =
715 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
716 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
717 struct sata_fis_h2d *cfis = &h2d;
718 u8 port = probe_ent->hard_port_no;
723 memset(cfis, 0, sizeof(struct sata_fis_h2d));
725 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
726 cfis->pm_port_c = 0x80; /* is command */
728 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
731 cfis->lba_high_exp = (block >> 40) & 0xff;
732 cfis->lba_mid_exp = (block >> 32) & 0xff;
733 cfis->lba_low_exp = (block >> 24) & 0xff;
734 cfis->lba_high = (block >> 16) & 0xff;
735 cfis->lba_mid = (block >> 8) & 0xff;
736 cfis->lba_low = block & 0xff;
737 cfis->device = ATA_LBA;
738 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
739 cfis->sector_count = blkcnt & 0xff;
741 if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer,
742 ATA_SECT_SIZE * blkcnt, is_write) > 0)
748 u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
749 u8 *buffer, int is_write)
751 struct ahci_probe_ent *probe_ent =
752 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
753 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
754 struct sata_fis_h2d *cfis = &h2d;
755 u8 port = probe_ent->hard_port_no;
758 if (sata_dev_desc[dev].lba48 != 1) {
759 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
765 memset(cfis, 0, sizeof(struct sata_fis_h2d));
767 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
768 cfis->pm_port_c = 0x80; /* is command */
770 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
771 : ATA_CMD_FPDMA_READ;
773 cfis->lba_high_exp = (block >> 40) & 0xff;
774 cfis->lba_mid_exp = (block >> 32) & 0xff;
775 cfis->lba_low_exp = (block >> 24) & 0xff;
776 cfis->lba_high = (block >> 16) & 0xff;
777 cfis->lba_mid = (block >> 8) & 0xff;
778 cfis->lba_low = block & 0xff;
780 cfis->device = ATA_LBA;
781 cfis->features_exp = (blkcnt >> 8) & 0xff;
782 cfis->features = blkcnt & 0xff;
784 /* Use the latest queue */
785 ahci_exec_ata_cmd(probe_ent, port, cfis,
786 buffer, ATA_SECT_SIZE * blkcnt, is_write);
791 void dwc_ahsata_flush_cache_ext(int dev)
793 struct ahci_probe_ent *probe_ent =
794 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
795 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
796 struct sata_fis_h2d *cfis = &h2d;
797 u8 port = probe_ent->hard_port_no;
799 memset(cfis, 0, sizeof(struct sata_fis_h2d));
801 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
802 cfis->pm_port_c = 0x80; /* is command */
803 cfis->command = ATA_CMD_FLUSH_EXT;
805 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
808 static void dwc_ahsata_init_wcache(int dev, u16 *id)
810 struct ahci_probe_ent *probe_ent =
811 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
813 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
814 probe_ent->flags |= SATA_FLAG_WCACHE;
815 if (ata_id_has_flush(id))
816 probe_ent->flags |= SATA_FLAG_FLUSH;
817 if (ata_id_has_flush_ext(id))
818 probe_ent->flags |= SATA_FLAG_FLUSH_EXT;
821 u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
822 const void *buffer, int is_write)
832 max_blks = ATA_MAX_SECTORS_LBA48;
835 if (blks > max_blks) {
836 if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start,
837 max_blks, addr, is_write))
841 addr += ATA_SECT_SIZE * max_blks;
843 if (blks != dwc_ahsata_rw_cmd_ext(dev, start,
844 blks, addr, is_write))
848 addr += ATA_SECT_SIZE * blks;
855 u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
856 const void *buffer, int is_write)
866 max_blks = ATA_MAX_SECTORS;
868 if (blks > max_blks) {
869 if (max_blks != dwc_ahsata_rw_cmd(dev, start,
870 max_blks, addr, is_write))
874 addr += ATA_SECT_SIZE * max_blks;
876 if (blks != dwc_ahsata_rw_cmd(dev, start,
877 blks, addr, is_write))
881 addr += ATA_SECT_SIZE * blks;
888 int sata_port_status(int dev, int port)
890 struct sata_port_regs *port_mmio;
891 struct ahci_probe_ent *probe_ent = NULL;
893 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
896 if (sata_dev_desc[dev].priv == NULL)
899 probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
900 port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
902 return readl(&(port_mmio->ssts)) & SATA_PORT_SSTS_DET_MASK;
906 * SATA interface between low level driver and command layer
908 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
912 if (sata_dev_desc[dev].lba48)
913 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
916 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
921 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
924 struct ahci_probe_ent *probe_ent =
925 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
926 u32 flags = probe_ent->flags;
928 if (sata_dev_desc[dev].lba48) {
929 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
931 if ((flags & SATA_FLAG_WCACHE) &&
932 (flags & SATA_FLAG_FLUSH_EXT))
933 dwc_ahsata_flush_cache_ext(dev);
935 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
937 if ((flags & SATA_FLAG_WCACHE) &&
938 (flags & SATA_FLAG_FLUSH))
939 dwc_ahsata_flush_cache(dev);
944 int scan_sata(int dev)
946 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
947 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
948 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
951 struct ahci_probe_ent *probe_ent =
952 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
953 u8 port = probe_ent->hard_port_no;
954 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
956 id = (u16 *)memalign(ARCH_DMA_MINALIGN,
957 roundup(ARCH_DMA_MINALIGN,
958 (ATA_ID_WORDS * 2)));
960 printf("id malloc failed\n\r");
964 /* Identify device to get information */
965 dwc_ahsata_identify(dev, id);
968 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
969 memcpy(pdev->product, serial, sizeof(serial));
971 /* Firmware version */
972 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
973 memcpy(pdev->revision, firmware, sizeof(firmware));
976 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
977 memcpy(pdev->vendor, product, sizeof(product));
980 n_sectors = ata_id_n_sectors(id);
981 pdev->lba = (u32)n_sectors;
983 pdev->type = DEV_TYPE_HARDDISK;
984 pdev->blksz = ATA_SECT_SIZE;
987 /* Check if support LBA48 */
988 if (ata_id_has_lba48(id)) {
990 debug("Device support LBA48\n\r");
993 /* Get the NCQ queue depth from device */
994 probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK);
995 probe_ent->flags |= ata_id_queue_depth(id);
997 /* Get the xfer mode from device */
998 dwc_ahsata_xfer_mode(dev, id);
1000 /* Get the write cache status from device */
1001 dwc_ahsata_init_wcache(dev, id);
1003 /* Set the xfer mode to highest speed */
1004 ahci_set_feature(dev, port);
1008 dwc_ahsata_print_info(dev);