2 * Copyright (C) Procsys. All rights reserved.
3 * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4 * <mushtaqk_921@yahoo.co.in>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * with the reference to ata_piix driver in kernel 2.4.32
25 * This file contains SATA controller and SATA drive initialization functions
33 #include <asm/byteorder.h>
39 #define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */
42 #define DRV_DECL /* For file specific declarations */
45 /* Macros realted to PCI */
46 #define PCI_SATA_BUS 0x00
47 #define PCI_SATA_DEV 0x1f
48 #define PCI_SATA_FUNC 0x02
50 #define PCI_SATA_BASE1 0x10
51 #define PCI_SATA_BASE2 0x14
52 #define PCI_SATA_BASE3 0x18
53 #define PCI_SATA_BASE4 0x1c
54 #define PCI_SATA_BASE5 0x20
58 #define PCI_DMA_CTL 0x48
60 #define PORT_PRESENT (1<<0)
61 #define PORT_ENABLED (1<<4)
64 u32 iobase1; /* Primary cmd block */
65 u32 iobase2; /* Primary ctl block */
66 u32 iobase3; /* Sec cmd block */
67 u32 iobase4; /* sec ctl block */
68 u32 iobase5; /* BMDMA*/
70 int pci_sata_init(void)
72 u32 bus = PCI_SATA_BUS;
73 u32 dev = PCI_SATA_DEV;
74 u32 fun = PCI_SATA_FUNC;
76 u8 lat = 0, pcibios_max_latency = 0xff;
77 u8 pmr; /* Port mapping reg */
78 u8 pi; /* Prgming Interface reg */
80 bdf = PCI_BDF(bus, dev, fun);
81 pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1);
82 pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2);
83 pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3);
84 pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4);
85 pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5);
87 if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
88 (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
89 (iobase5 == 0xFFFFFFFF)) {
91 printf("error no base addr for SATA controller\n");
95 iobase1 &= 0xFFFFFFFE;
96 iobase2 &= 0xFFFFFFFE;
97 iobase3 &= 0xFFFFFFFE;
98 iobase4 &= 0xFFFFFFFE;
99 iobase5 &= 0xFFFFFFFE;
102 pci_read_config_byte(bdf, PCI_PMR, &pmr);
104 puts("combined mode not supported\n");
108 pci_read_config_byte(bdf, PCI_PI, &pi);
109 if ((pi & 0x05) != 0x05) {
110 puts("Sata is in Legacy mode\n");
113 puts("sata is in Native mode\n");
115 /* MASTER CFG AND IO CFG */
116 pci_read_config_word(bdf, PCI_COMMAND, &cmd);
117 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
118 pci_write_config_word(bdf, PCI_COMMAND, cmd);
119 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
122 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
123 else if (lat > pcibios_max_latency)
124 lat = pcibios_max_latency;
125 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
130 int sata_bus_probe(int port_no)
135 mask = (PORT_PRESENT << port_no);
136 pci_read_config_word(bdf, PCI_PCS, &pcs);
137 orig_mask = (int) pcs & 0xff;
138 if ((orig_mask & mask) != mask)
144 int init_sata(int dev)
154 rv = pci_sata_init();
156 puts("pci initialization failed\n");
161 port[0].ioaddr.cmd_addr = iobase1;
162 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
163 iobase2 | ATA_PCI_CTL_OFS;
164 port[0].ioaddr.bmdma_addr = iobase5;
167 port[1].ioaddr.cmd_addr = iobase3;
168 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
169 iobase4 | ATA_PCI_CTL_OFS;
170 port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
172 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
173 sata_port(&port[i].ioaddr);
175 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
176 if (!(sata_bus_probe(i))) {
177 port[i].port_state = 0;
178 printf("SATA#%d port is not present\n", i);
180 printf("SATA#%d port is present\n", i);
181 if (sata_bus_softreset(i))
182 port[i].port_state = 0;
184 port[i].port_state = 1;
188 for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
191 if (port[i].port_state == 0)
193 for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
195 set_Feature_cmd(i, j);
196 devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
197 if ((sata_dev_desc[devno].lba > 0) &&
198 (sata_dev_desc[devno].blksz > 0)) {
199 dev_print(&sata_dev_desc[devno]);
200 /* initialize partition type */
201 init_part(&sata_dev_desc[devno]);
208 static inline u8 sata_inb(unsigned long ioaddr)
213 static inline void sata_outb(unsigned char val, unsigned long ioaddr)
218 static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf,
221 outsw(ioaddr->data_addr, sect_buf, words << 1);
224 static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words)
226 insw(ioaddr->data_addr, sect_buf, words << 1);
230 static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len)
232 unsigned char *end, *last;
237 /* reserve space for '\0' */
241 /* skip leading white space */
242 while ((*src) && (src < end) && (*src == ' '))
245 /* copy string, omitting trailing white space */
246 while ((*src) && (src < end)) {
255 int sata_bus_softreset(int num)
257 u8 dev = 0, status = 0, i;
259 port[num].dev_mask = 0;
261 for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
262 if (!(sata_devchk(&port[num].ioaddr, i))) {
263 debug("dev_chk failed for dev#%d\n", i);
265 port[num].dev_mask |= (1 << i);
266 debug("dev_chk passed for dev#%d\n", i);
270 if (!(port[num].dev_mask)) {
271 printf("no devices on port%d\n", num);
275 dev_select(&port[num].ioaddr, dev);
277 port[num].ctl_reg = 0x08; /* Default value of control reg */
278 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
280 sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
282 sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
285 * spec mandates ">= 2ms" before checking status.
286 * We wait 150ms, because that was the magic delay used for
287 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
288 * between when the ATA command register is written, and then
289 * status is checked. Because waiting for "a while" before
290 * checking status is fine, post SRST, we perform this magic
291 * delay here as well.
294 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300);
295 while ((status & ATA_BUSY)) {
297 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3);
300 if (status & ATA_BUSY)
301 printf("ata%u is slow to respond,plz be patient\n", num);
303 while ((status & ATA_BUSY)) {
305 status = sata_chk_status(&port[num].ioaddr);
308 if (status & ATA_BUSY) {
309 printf("ata%u failed to respond : bus reset failed\n", num);
315 void sata_identify(int num, int dev)
317 u8 cmd = 0, status = 0;
318 u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
319 u16 iobuf[ATA_SECT_SIZE];
323 memset(iobuf, 0, sizeof(iobuf));
324 hd_driveid_t *iop = (hd_driveid_t *) iobuf;
331 if (!(port[num].dev_mask & mask)) {
332 printf("dev%d is not present on port#%d\n", dev, num);
336 printf("port=%d dev=%d\n", num, dev);
338 dev_select(&port[num].ioaddr, dev);
341 cmd = ATA_CMD_IDENT; /* Device Identify Command */
342 sata_outb(cmd, port[num].ioaddr.command_addr);
343 sata_inb(port[num].ioaddr.altstatus_addr);
346 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000);
347 if (status & ATA_ERR) {
348 puts("\ndevice not responding\n");
349 port[num].dev_mask &= ~mask;
353 input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
355 debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
356 "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
357 iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
358 iobuf[87], iobuf[88]);
360 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
361 if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
362 debug("ata%u: no dma/lba\n", num);
365 if (ata_id_has_lba48(iobuf))
366 n_sectors = ata_id_u64(iobuf, 100);
368 n_sectors = ata_id_u32(iobuf, 60);
369 debug("no. of sectors %u\n", ata_id_u64(iobuf, 100));
370 debug("no. of sectors %u\n", ata_id_u32(iobuf, 60));
372 if (n_sectors == 0) {
373 port[num].dev_mask &= ~mask;
377 sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
378 sizeof(sata_dev_desc[devno].revision));
379 sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
380 sizeof(sata_dev_desc[devno].vendor));
381 sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
382 sizeof(sata_dev_desc[devno].product));
383 strswab(sata_dev_desc[devno].revision);
384 strswab(sata_dev_desc[devno].vendor);
386 if ((iop->config & 0x0080) == 0x0080)
387 sata_dev_desc[devno].removable = 1;
389 sata_dev_desc[devno].removable = 0;
391 sata_dev_desc[devno].lba = iop->lba_capacity;
392 debug("lba=0x%x", sata_dev_desc[devno].lba);
395 if (iop->command_set_2 & 0x0400) {
396 sata_dev_desc[devno].lba48 = 1;
397 lba = (unsigned long long) iop->lba48_capacity[0] |
398 ((unsigned long long) iop->lba48_capacity[1] << 16) |
399 ((unsigned long long) iop->lba48_capacity[2] << 32) |
400 ((unsigned long long) iop->lba48_capacity[3] << 48);
402 sata_dev_desc[devno].lba48 = 0;
407 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
408 sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
409 sata_dev_desc[devno].log2blksz = LOG2(sata_dev_desc[devno].blksz);
410 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
413 void set_Feature_cmd(int num, int dev)
415 u8 mask = 0x00, status = 0;
422 if (!(port[num].dev_mask & mask)) {
423 debug("dev%d is not present on port#%d\n", dev, num);
427 dev_select(&port[num].ioaddr, dev);
429 sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr);
430 sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr);
431 sata_outb(0, port[num].ioaddr.lbal_addr);
432 sata_outb(0, port[num].ioaddr.lbam_addr);
433 sata_outb(0, port[num].ioaddr.lbah_addr);
435 sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
436 sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr);
441 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000);
442 if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
443 printf("Error : status 0x%02x\n", status);
444 port[num].dev_mask &= ~mask;
448 void sata_port(struct sata_ioports *ioport)
450 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
451 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
452 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
453 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
454 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
455 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
456 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
457 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
458 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
459 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
462 int sata_devchk(struct sata_ioports *ioaddr, int dev)
466 dev_select(ioaddr, dev);
468 sata_outb(0x55, ioaddr->nsect_addr);
469 sata_outb(0xaa, ioaddr->lbal_addr);
471 sata_outb(0xaa, ioaddr->nsect_addr);
472 sata_outb(0x55, ioaddr->lbal_addr);
474 sata_outb(0x55, ioaddr->nsect_addr);
475 sata_outb(0xaa, ioaddr->lbal_addr);
477 nsect = sata_inb(ioaddr->nsect_addr);
478 lbal = sata_inb(ioaddr->lbal_addr);
480 if ((nsect == 0x55) && (lbal == 0xaa))
481 return 1; /* we found a device */
483 return 0; /* nothing found */
486 void dev_select(struct sata_ioports *ioaddr, int dev)
491 tmp = ATA_DEVICE_OBS;
493 tmp = ATA_DEVICE_OBS | ATA_DEV1;
495 sata_outb(tmp, ioaddr->device_addr);
496 sata_inb(ioaddr->altstatus_addr);
500 u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max)
506 status = sata_chk_status(ioaddr);
508 } while ((status & bits) && (max > 0));
513 u8 sata_chk_status(struct sata_ioports *ioaddr)
515 return sata_inb(ioaddr->status_addr);
519 ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff)
521 ulong n = 0, *buffer = (ulong *)buff;
522 u8 dev = 0, num = 0, mask = 0, status = 0;
525 unsigned char lba48 = 0;
527 if (blknr & 0x0000fffff0000000) {
528 if (!sata_dev_desc[devno].lba48) {
529 printf("Drive doesn't support 48-bit addressing\n");
532 /* more than 28 bits used, use 48bit mode */
537 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
538 /* dev on the port */
539 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
540 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
549 if (!(port[num].dev_mask & mask)) {
550 printf("dev%d is not present on port#%d\n", dev, num);
555 dev_select(&port[num].ioaddr, dev);
557 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
558 if (status & ATA_BUSY) {
559 printf("ata%u failed to respond\n", port[num].port_no);
562 while (blkcnt-- > 0) {
563 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
564 if (status & ATA_BUSY) {
565 printf("ata%u failed to respond\n", 0);
570 /* write high bits */
571 sata_outb(0, port[num].ioaddr.nsect_addr);
572 sata_outb((blknr >> 24) & 0xFF,
573 port[num].ioaddr.lbal_addr);
574 sata_outb((blknr >> 32) & 0xFF,
575 port[num].ioaddr.lbam_addr);
576 sata_outb((blknr >> 40) & 0xFF,
577 port[num].ioaddr.lbah_addr);
580 sata_outb(1, port[num].ioaddr.nsect_addr);
581 sata_outb(((blknr) >> 0) & 0xFF,
582 port[num].ioaddr.lbal_addr);
583 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
584 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
588 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
589 sata_outb(ATA_CMD_READ_EXT,
590 port[num].ioaddr.command_addr);
594 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
595 port[num].ioaddr.device_addr);
596 sata_outb(ATA_CMD_READ,
597 port[num].ioaddr.command_addr);
601 /* may take up to 4 sec */
602 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
604 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
608 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
609 device, (ulong) blknr, status);
610 err = sata_inb(port[num].ioaddr.error_addr);
611 printf("Error reg = 0x%x\n", err);
614 input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
615 sata_inb(port[num].ioaddr.altstatus_addr);
620 buffer += ATA_SECTORWORDS;
625 ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buff)
627 ulong n = 0, *buffer = (ulong *)buff;
628 unsigned char status = 0, num = 0, dev = 0, mask = 0;
631 unsigned char lba48 = 0;
633 if (blknr & 0x0000fffff0000000) {
634 if (!sata_dev_desc[devno].lba48) {
635 printf("Drive doesn't support 48-bit addressing\n");
638 /* more than 28 bits used, use 48bit mode */
643 num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
644 /* dev on the Port */
645 if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
646 dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
656 dev_select(&port[num].ioaddr, dev);
658 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
659 if (status & ATA_BUSY) {
660 printf("ata%u failed to respond\n", port[num].port_no);
664 while (blkcnt-- > 0) {
665 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
666 if (status & ATA_BUSY) {
667 printf("ata%u failed to respond\n",
673 /* write high bits */
674 sata_outb(0, port[num].ioaddr.nsect_addr);
675 sata_outb((blknr >> 24) & 0xFF,
676 port[num].ioaddr.lbal_addr);
677 sata_outb((blknr >> 32) & 0xFF,
678 port[num].ioaddr.lbam_addr);
679 sata_outb((blknr >> 40) & 0xFF,
680 port[num].ioaddr.lbah_addr);
683 sata_outb(1, port[num].ioaddr.nsect_addr);
684 sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
685 sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
686 sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
689 sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
690 sata_outb(ATA_CMD_WRITE_EXT,
691 port[num].ioaddr.command_addr);
695 sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
696 port[num].ioaddr.device_addr);
697 sata_outb(ATA_CMD_WRITE,
698 port[num].ioaddr.command_addr);
702 /* may take up to 4 sec */
703 status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
704 if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
706 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
707 device, (ulong) blknr, status);
711 output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
712 sata_inb(port[num].ioaddr.altstatus_addr);
717 buffer += ATA_SECTORWORDS;
722 int scan_sata(int dev)