2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
14 #include <asm/processor.h>
15 #include <asm/errno.h>
20 #include <linux/ctype.h>
23 static int ata_io_flush(u8 port);
25 struct ahci_probe_ent *probe_ent = NULL;
26 hd_driveid_t *ataid[AHCI_MAX_PORTS];
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 10000
42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 4
46 static inline u32 ahci_port_base(u32 base, u32 port)
48 return base + 0x100 + (port * 0x80);
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
55 base = ahci_port_base(base, port_idx);
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
62 #define msleep(a) udelay(a * 1000)
64 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
97 static int waiting_for_cmd_completed(volatile u8 *offset,
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
107 return (i < timeout_msec) ? 0 : -1;
111 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
113 #ifndef CONFIG_SCSI_AHCI_PLAT
114 pci_dev_t pdev = probe_ent->dev;
116 unsigned short vendor;
118 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
119 u32 tmp, cap_save, cmd;
121 volatile u8 *port_mmio;
123 debug("ahci_host_init: start\n");
125 cap_save = readl(mmio + HOST_CAP);
126 cap_save &= ((1 << 28) | (1 << 17));
127 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
129 /* global controller reset */
130 tmp = readl(mmio + HOST_CTL);
131 if ((tmp & HOST_RESET) == 0)
132 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
134 /* reset must complete within 1 second, or
135 * the hardware should be considered fried.
140 tmp = readl(mmio + HOST_CTL);
142 debug("controller reset failed (0x%x)\n", tmp);
145 } while (tmp & HOST_RESET);
147 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
148 writel(cap_save, mmio + HOST_CAP);
149 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
151 #ifndef CONFIG_SCSI_AHCI_PLAT
152 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
154 if (vendor == PCI_VENDOR_ID_INTEL) {
156 pci_read_config_word(pdev, 0x92, &tmp16);
158 pci_write_config_word(pdev, 0x92, tmp16);
161 probe_ent->cap = readl(mmio + HOST_CAP);
162 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
163 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
165 debug("cap 0x%x port_map 0x%x n_ports %d\n",
166 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
168 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
169 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
171 for (i = 0; i < probe_ent->n_ports; i++) {
172 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
173 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
174 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
176 /* make sure port is not active */
177 tmp = readl(port_mmio + PORT_CMD);
178 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
179 PORT_CMD_FIS_RX | PORT_CMD_START)) {
180 debug("Port %d is active. Deactivating.\n", i);
181 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
182 PORT_CMD_FIS_RX | PORT_CMD_START);
183 writel_with_flush(tmp, port_mmio + PORT_CMD);
185 /* spec says 500 msecs for each bit, so
186 * this is slightly incorrect.
191 /* Add the spinup command to whatever mode bits may
192 * already be on in the command register.
194 cmd = readl(port_mmio + PORT_CMD);
195 cmd |= PORT_CMD_FIS_RX;
196 cmd |= PORT_CMD_SPIN_UP;
197 writel_with_flush(cmd, port_mmio + PORT_CMD);
199 /* Bring up SATA link.
200 * SATA link bringup time is usually less than 1 ms; only very
201 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
204 while (j < WAIT_MS_LINKUP) {
205 tmp = readl(port_mmio + PORT_SCR_STAT);
206 if ((tmp & 0xf) == 0x3)
211 if (j == WAIT_MS_LINKUP) {
212 printf("SATA link %d timeout.\n", i);
215 debug("SATA link ok.\n");
218 /* Clear error status */
219 tmp = readl(port_mmio + PORT_SCR_ERR);
221 writel(tmp, port_mmio + PORT_SCR_ERR);
223 debug("Spinning up device on SATA port %d... ", i);
226 while (j < WAIT_MS_SPINUP) {
227 tmp = readl(port_mmio + PORT_TFDATA);
228 if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))
233 printf("Target spinup took %d ms.\n", j);
234 if (j == WAIT_MS_SPINUP)
239 tmp = readl(port_mmio + PORT_SCR_ERR);
240 debug("PORT_SCR_ERR 0x%x\n", tmp);
241 writel(tmp, port_mmio + PORT_SCR_ERR);
243 /* ack any pending irq events for this port */
244 tmp = readl(port_mmio + PORT_IRQ_STAT);
245 debug("PORT_IRQ_STAT 0x%x\n", tmp);
247 writel(tmp, port_mmio + PORT_IRQ_STAT);
249 writel(1 << i, mmio + HOST_IRQ_STAT);
251 /* set irq mask (enables interrupts) */
252 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
254 /* register linkup ports */
255 tmp = readl(port_mmio + PORT_SCR_STAT);
256 debug("SATA port %d status: 0x%x\n", i, tmp);
257 if ((tmp & 0xf) == 0x03)
258 probe_ent->link_port_map |= (0x01 << i);
261 tmp = readl(mmio + HOST_CTL);
262 debug("HOST_CTL 0x%x\n", tmp);
263 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
264 tmp = readl(mmio + HOST_CTL);
265 debug("HOST_CTL 0x%x\n", tmp);
266 #ifndef CONFIG_SCSI_AHCI_PLAT
267 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
268 tmp |= PCI_COMMAND_MASTER;
269 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
275 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
277 #ifndef CONFIG_SCSI_AHCI_PLAT
278 pci_dev_t pdev = probe_ent->dev;
281 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
282 u32 vers, cap, cap2, impl, speed;
286 vers = readl(mmio + HOST_VERSION);
287 cap = probe_ent->cap;
288 cap2 = readl(mmio + HOST_CAP2);
289 impl = probe_ent->port_map;
291 speed = (cap >> 20) & 0xf;
301 #ifdef CONFIG_SCSI_AHCI_PLAT
304 pci_read_config_word(pdev, 0x0a, &cc);
307 else if (cc == 0x0106)
309 else if (cc == 0x0104)
314 printf("AHCI %02x%02x.%02x%02x "
315 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
320 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
326 cap & (1 << 31) ? "64bit " : "",
327 cap & (1 << 30) ? "ncq " : "",
328 cap & (1 << 28) ? "ilck " : "",
329 cap & (1 << 27) ? "stag " : "",
330 cap & (1 << 26) ? "pm " : "",
331 cap & (1 << 25) ? "led " : "",
332 cap & (1 << 24) ? "clo " : "",
333 cap & (1 << 19) ? "nz " : "",
334 cap & (1 << 18) ? "only " : "",
335 cap & (1 << 17) ? "pmp " : "",
336 cap & (1 << 16) ? "fbss " : "",
337 cap & (1 << 15) ? "pio " : "",
338 cap & (1 << 14) ? "slum " : "",
339 cap & (1 << 13) ? "part " : "",
340 cap & (1 << 7) ? "ccc " : "",
341 cap & (1 << 6) ? "ems " : "",
342 cap & (1 << 5) ? "sxs " : "",
343 cap2 & (1 << 2) ? "apst " : "",
344 cap2 & (1 << 1) ? "nvmp " : "",
345 cap2 & (1 << 0) ? "boh " : "");
348 #ifndef CONFIG_SCSI_AHCI_PLAT
349 static int ahci_init_one(pci_dev_t pdev)
354 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
356 probe_ent = malloc(sizeof(struct ahci_probe_ent));
357 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
358 probe_ent->dev = pdev;
360 probe_ent->host_flags = ATA_FLAG_SATA
365 probe_ent->pio_mask = 0x1f;
366 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
368 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
369 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
372 * JMicron-specific fixup:
373 * make sure we're in AHCI mode
375 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
376 if (vendor == 0x197b)
377 pci_write_config_byte(pdev, 0x41, 0xa1);
379 /* initialize adapter */
380 rc = ahci_host_init(probe_ent);
384 ahci_print_info(probe_ent);
393 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
395 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
397 struct ahci_ioports *pp = &(probe_ent->port[port]);
398 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
402 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
403 if (sg_count > AHCI_MAX_SG) {
404 printf("Error:Too much sg!\n");
408 for (i = 0; i < sg_count; i++) {
410 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
411 ahci_sg->addr_hi = 0;
412 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
413 (buf_len < MAX_DATA_BYTE_COUNT
415 : (MAX_DATA_BYTE_COUNT - 1)));
417 buf_len -= MAX_DATA_BYTE_COUNT;
424 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
426 pp->cmd_slot->opts = cpu_to_le32(opts);
427 pp->cmd_slot->status = 0;
428 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
429 pp->cmd_slot->tbl_addr_hi = 0;
433 #ifdef CONFIG_AHCI_SETFEATURES_XFER
434 static void ahci_set_feature(u8 port)
436 struct ahci_ioports *pp = &(probe_ent->port[port]);
437 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
438 u32 cmd_fis_len = 5; /* five dwords */
442 memset(fis, 0, sizeof(fis));
445 fis[2] = ATA_CMD_SETF;
446 fis[3] = SETFEATURES_XFER;
447 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
449 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
450 ahci_fill_cmd_slot(pp, cmd_fis_len);
451 ahci_dcache_flush_sata_cmd(pp);
452 writel(1, port_mmio + PORT_CMD_ISSUE);
453 readl(port_mmio + PORT_CMD_ISSUE);
455 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
456 WAIT_MS_DATAIO, 0x1)) {
457 printf("set feature error on port %d!\n", port);
463 static int ahci_port_start(u8 port)
465 struct ahci_ioports *pp = &(probe_ent->port[port]);
466 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
470 debug("Enter start port: %d\n", port);
471 port_status = readl(port_mmio + PORT_SCR_STAT);
472 debug("Port %d status: %x\n", port, port_status);
473 if ((port_status & 0xf) != 0x03) {
474 printf("No Link on this port!\n");
478 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
481 printf("No mem for table!\n");
485 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
486 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
489 * First item in chunk of DMA memory: 32-slot command table,
490 * 32 bytes each in size
493 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
494 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
495 mem += (AHCI_CMD_SLOT_SZ + 224);
498 * Second item: Received-FIS area
500 pp->rx_fis = virt_to_phys((void *)mem);
501 mem += AHCI_RX_FIS_SZ;
504 * Third item: data area for storing a single command
505 * and its scatter-gather table
507 pp->cmd_tbl = virt_to_phys((void *)mem);
508 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
510 mem += AHCI_CMD_TBL_HDR;
512 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
514 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
516 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
518 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
519 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
520 PORT_CMD_START, port_mmio + PORT_CMD);
522 debug("Exit start port %d\n", port);
528 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
529 int buf_len, u8 is_write)
532 struct ahci_ioports *pp = &(probe_ent->port[port]);
533 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
538 debug("Enter %s: for port %d\n", __func__, port);
540 if (port > probe_ent->n_ports) {
541 printf("Invalid port number %d\n", port);
545 port_status = readl(port_mmio + PORT_SCR_STAT);
546 if ((port_status & 0xf) != 0x03) {
547 debug("No Link on port %d!\n", port);
551 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
553 sg_count = ahci_fill_sg(port, buf, buf_len);
554 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
555 ahci_fill_cmd_slot(pp, opts);
557 ahci_dcache_flush_sata_cmd(pp);
558 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
560 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
562 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
563 WAIT_MS_DATAIO, 0x1)) {
564 printf("timeout exit!\n");
568 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
569 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
575 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
578 for (i = 0; i < len / 2; i++)
579 target[i] = swab16(src[i]);
580 return (char *)target;
584 static void dump_ataid(hd_driveid_t *ataid)
586 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
587 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
588 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
589 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
590 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
591 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
592 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
593 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
594 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
595 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
596 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
597 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
598 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
599 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
600 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
605 * SCSI INQUIRY command operation.
607 static int ata_scsiop_inquiry(ccb *pccb)
612 0x5, /* claim SPC-3 version compatibility */
620 /* Clean ccb data buffer */
621 memset(pccb->pdata, 0, pccb->datalen);
623 memcpy(pccb->pdata, hdr, sizeof(hdr));
625 if (pccb->datalen <= 35)
628 memset(fis, 0, sizeof(fis));
629 /* Construct the FIS */
630 fis[0] = 0x27; /* Host to device FIS. */
631 fis[1] = 1 << 7; /* Command FIS. */
632 fis[2] = ATA_CMD_IDENT; /* Command byte. */
634 /* Read id from sata */
636 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
639 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
640 sizeof(hd_driveid_t), 0)) {
641 debug("scsi_ahci: SCSI inquiry command failure.\n");
647 ataid[port] = (hd_driveid_t *) tmpid;
649 memcpy(&pccb->pdata[8], "ATA ", 8);
650 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
651 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
653 dump_ataid(ataid[port]);
659 * SCSI READ10/WRITE10 command operation.
661 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
666 u8 *user_buffer = pccb->pdata;
667 u32 user_buffer_size = pccb->datalen;
669 /* Retrieve the base LBA number from the ccb structure. */
670 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
671 lba = be32_to_cpu(lba);
674 * And the number of blocks.
676 * For 10-byte and 16-byte SCSI R/W commands, transfer
677 * length 0 means transfer 0 block of data.
678 * However, for ATA R/W commands, sector count 0 means
679 * 256 or 65536 sectors, not 0 sectors as in SCSI.
681 * WARNING: one or two older ATA drives treat 0 as 0...
683 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
685 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
686 is_write ? "write" : "read", (unsigned)lba, blocks);
689 memset(fis, 0, sizeof(fis));
690 fis[0] = 0x27; /* Host to device FIS. */
691 fis[1] = 1 << 7; /* Command FIS. */
692 /* Command byte (read/write). */
693 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
696 u16 now_blocks; /* number of blocks per iteration */
697 u32 transfer_size; /* number of bytes per iteration */
699 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
701 transfer_size = ATA_BLOCKSIZE * now_blocks;
702 if (transfer_size > user_buffer_size) {
703 printf("scsi_ahci: Error: buffer too small.\n");
707 /* LBA48 SATA command but only use 32bit address range within
708 * that. The next smaller command range (28bit) is too small.
710 fis[4] = (lba >> 0) & 0xff;
711 fis[5] = (lba >> 8) & 0xff;
712 fis[6] = (lba >> 16) & 0xff;
713 fis[7] = 1 << 6; /* device reg: set LBA mode */
714 fis[8] = ((lba >> 24) & 0xff);
715 fis[3] = 0xe0; /* features */
717 /* Block (sector) count */
718 fis[12] = (now_blocks >> 0) & 0xff;
719 fis[13] = (now_blocks >> 8) & 0xff;
721 /* Read/Write from ahci */
722 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
723 user_buffer, user_buffer_size,
725 debug("scsi_ahci: SCSI %s10 command failure.\n",
726 is_write ? "WRITE" : "READ");
730 /* If this transaction is a write, do a following flush.
731 * Writes in u-boot are so rare, and the logic to know when is
732 * the last write and do a flush only there is sufficiently
733 * difficult. Just do a flush after every write. This incurs,
734 * usually, one extra flush when the rare writes do happen.
737 if (-EIO == ata_io_flush(pccb->target))
740 user_buffer += transfer_size;
741 user_buffer_size -= transfer_size;
742 blocks -= now_blocks;
751 * SCSI READ CAPACITY10 command operation.
753 static int ata_scsiop_read_capacity10(ccb *pccb)
758 if (!ataid[pccb->target]) {
759 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
761 "\tPlease run SCSI commmand INQUIRY firstly!\n");
765 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
766 if (cap == 0xfffffff) {
767 unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
768 if (cap48[2] || cap48[3]) {
771 cap = (le16_to_cpu(cap48[1]) << 16) |
772 (le16_to_cpu(cap48[0]));
776 cap = cpu_to_be32(cap);
777 memcpy(pccb->pdata, &cap, sizeof(cap));
779 block_size = cpu_to_be32((u32)512);
780 memcpy(&pccb->pdata[4], &block_size, 4);
787 * SCSI READ CAPACITY16 command operation.
789 static int ata_scsiop_read_capacity16(ccb *pccb)
794 if (!ataid[pccb->target]) {
795 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
797 "\tPlease run SCSI commmand INQUIRY firstly!\n");
801 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
802 if (cap == 0xfffffff) {
803 memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
804 cap = le64_to_cpu(cap);
807 cap = cpu_to_be64(cap);
808 memcpy(pccb->pdata, &cap, sizeof(cap));
810 block_size = cpu_to_be64((u64)512);
811 memcpy(&pccb->pdata[8], &block_size, 8);
818 * SCSI TEST UNIT READY command operation.
820 static int ata_scsiop_test_unit_ready(ccb *pccb)
822 return (ataid[pccb->target]) ? 0 : -EPERM;
826 int scsi_exec(ccb *pccb)
830 switch (pccb->cmd[0]) {
832 ret = ata_scsiop_read_write(pccb, 0);
835 ret = ata_scsiop_read_write(pccb, 1);
837 case SCSI_RD_CAPAC10:
838 ret = ata_scsiop_read_capacity10(pccb);
840 case SCSI_RD_CAPAC16:
841 ret = ata_scsiop_read_capacity16(pccb);
844 ret = ata_scsiop_test_unit_ready(pccb);
847 ret = ata_scsiop_inquiry(pccb);
850 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
855 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
863 void scsi_low_level_init(int busdevfunc)
868 #ifndef CONFIG_SCSI_AHCI_PLAT
869 ahci_init_one(busdevfunc);
872 linkmap = probe_ent->link_port_map;
874 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
875 if (((linkmap >> i) & 0x01)) {
876 if (ahci_port_start((u8) i)) {
877 printf("Can not start port %d\n", i);
880 #ifdef CONFIG_AHCI_SETFEATURES_XFER
881 ahci_set_feature((u8) i);
887 #ifdef CONFIG_SCSI_AHCI_PLAT
888 int ahci_init(u32 base)
893 memset(ataid, 0, sizeof(ataid));
895 probe_ent = malloc(sizeof(struct ahci_probe_ent));
896 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
898 probe_ent->host_flags = ATA_FLAG_SATA
903 probe_ent->pio_mask = 0x1f;
904 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
906 probe_ent->mmio_base = base;
908 /* initialize adapter */
909 rc = ahci_host_init(probe_ent);
913 ahci_print_info(probe_ent);
915 linkmap = probe_ent->link_port_map;
917 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
918 if (((linkmap >> i) & 0x01)) {
919 if (ahci_port_start((u8) i)) {
920 printf("Can not start port %d\n", i);
923 #ifdef CONFIG_AHCI_SETFEATURES_XFER
924 ahci_set_feature((u8) i);
934 * In the general case of generic rotating media it makes sense to have a
935 * flush capability. It probably even makes sense in the case of SSDs because
936 * one cannot always know for sure what kind of internal cache/flush mechanism
937 * is embodied therein. At first it was planned to invoke this after the last
938 * write to disk and before rebooting. In practice, knowing, a priori, which
939 * is the last write is difficult. Because writing to the disk in u-boot is
940 * very rare, this flush command will be invoked after every block write.
942 static int ata_io_flush(u8 port)
945 struct ahci_ioports *pp = &(probe_ent->port[port]);
946 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
947 u32 cmd_fis_len = 5; /* five dwords */
951 fis[0] = 0x27; /* Host to device FIS. */
952 fis[1] = 1 << 7; /* Command FIS. */
953 fis[2] = ATA_CMD_FLUSH_EXT;
955 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
956 ahci_fill_cmd_slot(pp, cmd_fis_len);
957 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
959 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
960 WAIT_MS_FLUSH, 0x1)) {
961 debug("scsi_ahci: flush command timeout on port %d.\n", port);
969 void scsi_bus_reset(void)
975 void scsi_print_error(ccb * pccb)
977 /*The ahci error info can be read in the ahci driver*/