drivers/atm/idt77252.c

   1 /*******************************************************************
   2  *
   3  * Copyright (c) 2000 ATecoM GmbH
   4  *
   5  * The author may be reached at ecd@atecom.com.
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
  13  * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
  16  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18  * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the  GNU General Public License along
  24  * with this program; if not, write  to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *******************************************************************/
  28
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/poison.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/kernel.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/atmdev.h>
  37 #include <linux/atm.h>
  38 #include <linux/delay.h>
  39 #include <linux/init.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/bitops.h>
  42 #include <linux/wait.h>
  43 #include <linux/jiffies.h>
  44 #include <linux/mutex.h>
  45 #include <linux/slab.h>
  46
  47 #include <asm/io.h>
  48 #include <linux/uaccess.h>
  49 #include <linux/atomic.h>
  50 #include <asm/byteorder.h>
  51
  52 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
  53 #include "suni.h"
  54 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
  55
  56
  57 #include "idt77252.h"
  58 #include "idt77252_tables.h"
  59
  60 static unsigned int vpibits = 1;
  61
  62
  63 #define ATM_IDT77252_SEND_IDLE 1
  64
  65
  66 /*
  67  * Debug HACKs.
  68  */
  69 #define DEBUG_MODULE 1
  70 #undef HAVE_EEPROM      /* does not work, yet. */
  71
  72 #ifdef CONFIG_ATM_IDT77252_DEBUG
  73 static unsigned long debug = DBG_GENERAL;
  74 #endif
  75
  76
  77 #define SAR_RX_DELAY    (SAR_CFG_RXINT_NODELAY)
  78
  79
  80 /*
  81  * SCQ Handling.
  82  */
  83 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
  84 static void free_scq(struct idt77252_dev *, struct scq_info *);
  85 static int queue_skb(struct idt77252_dev *, struct vc_map *,
  86                      struct sk_buff *, int oam);
  87 static void drain_scq(struct idt77252_dev *, struct vc_map *);
  88 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
  89 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
  90
  91 /*
  92  * FBQ Handling.
  93  */
  94 static int push_rx_skb(struct idt77252_dev *,
  95                        struct sk_buff *, int queue);
  96 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
  97 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
  98 static void recycle_rx_pool_skb(struct idt77252_dev *,
  99                                 struct rx_pool *);
 100 static void add_rx_skb(struct idt77252_dev *, int queue,
 101                        unsigned int size, unsigned int count);
 102
 103 /*
 104  * RSQ Handling.
 105  */
 106 static int init_rsq(struct idt77252_dev *);
 107 static void deinit_rsq(struct idt77252_dev *);
 108 static void idt77252_rx(struct idt77252_dev *);
 109
 110 /*
 111  * TSQ handling.
 112  */
 113 static int init_tsq(struct idt77252_dev *);
 114 static void deinit_tsq(struct idt77252_dev *);
 115 static void idt77252_tx(struct idt77252_dev *);
 116
 117
 118 /*
 119  * ATM Interface.
 120  */
 121 static void idt77252_dev_close(struct atm_dev *dev);
 122 static int idt77252_open(struct atm_vcc *vcc);
 123 static void idt77252_close(struct atm_vcc *vcc);
 124 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
 125 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
 126                              int flags);
 127 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
 128                              unsigned long addr);
 129 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
 130 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
 131                                int flags);
 132 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
 133                               char *page);
 134 static void idt77252_softint(struct work_struct *work);
 135
 136
 137 static const struct atmdev_ops idt77252_ops =
 138 {
 139         .dev_close      = idt77252_dev_close,
 140         .open           = idt77252_open,
 141         .close          = idt77252_close,
 142         .send           = idt77252_send,
 143         .send_oam       = idt77252_send_oam,
 144         .phy_put        = idt77252_phy_put,
 145         .phy_get        = idt77252_phy_get,
 146         .change_qos     = idt77252_change_qos,
 147         .proc_read      = idt77252_proc_read,
 148         .owner          = THIS_MODULE
 149 };
 150
 151 static struct idt77252_dev *idt77252_chain = NULL;
 152 static unsigned int idt77252_sram_write_errors = 0;
 153
 154 /*****************************************************************************/
 155 /*                                                                           */
 156 /* I/O and Utility Bus                                                       */
 157 /*                                                                           */
 158 /*****************************************************************************/
 159
 160 static void
 161 waitfor_idle(struct idt77252_dev *card)
 162 {
 163         u32 stat;
 164
 165         stat = readl(SAR_REG_STAT);
 166         while (stat & SAR_STAT_CMDBZ)
 167                 stat = readl(SAR_REG_STAT);
 168 }
 169
 170 static u32
 171 read_sram(struct idt77252_dev *card, unsigned long addr)
 172 {
 173         unsigned long flags;
 174         u32 value;
 175
 176         spin_lock_irqsave(&card->cmd_lock, flags);
 177         writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
 178         waitfor_idle(card);
 179         value = readl(SAR_REG_DR0);
 180         spin_unlock_irqrestore(&card->cmd_lock, flags);
 181         return value;
 182 }
 183
 184 static void
 185 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
 186 {
 187         unsigned long flags;
 188
 189         if ((idt77252_sram_write_errors == 0) &&
 190             (((addr > card->tst[0] + card->tst_size - 2) &&
 191               (addr < card->tst[0] + card->tst_size)) ||
 192              ((addr > card->tst[1] + card->tst_size - 2) &&
 193               (addr < card->tst[1] + card->tst_size)))) {
 194                 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
 195                        card->name, addr, value);
 196         }
 197
 198         spin_lock_irqsave(&card->cmd_lock, flags);
 199         writel(value, SAR_REG_DR0);
 200         writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
 201         waitfor_idle(card);
 202         spin_unlock_irqrestore(&card->cmd_lock, flags);
 203 }
 204
 205 static u8
 206 read_utility(void *dev, unsigned long ubus_addr)
 207 {
 208         struct idt77252_dev *card = dev;
 209         unsigned long flags;
 210         u8 value;
 211
 212         if (!card) {
 213                 printk("Error: No such device.\n");
 214                 return -1;
 215         }
 216
 217         spin_lock_irqsave(&card->cmd_lock, flags);
 218         writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
 219         waitfor_idle(card);
 220         value = readl(SAR_REG_DR0);
 221         spin_unlock_irqrestore(&card->cmd_lock, flags);
 222         return value;
 223 }
 224
 225 static void
 226 write_utility(void *dev, unsigned long ubus_addr, u8 value)
 227 {
 228         struct idt77252_dev *card = dev;
 229         unsigned long flags;
 230
 231         if (!card) {
 232                 printk("Error: No such device.\n");
 233                 return;
 234         }
 235
 236         spin_lock_irqsave(&card->cmd_lock, flags);
 237         writel((u32) value, SAR_REG_DR0);
 238         writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
 239         waitfor_idle(card);
 240         spin_unlock_irqrestore(&card->cmd_lock, flags);
 241 }
 242
 243 #ifdef HAVE_EEPROM
 244 static u32 rdsrtab[] =
 245 {
 246         SAR_GP_EECS | SAR_GP_EESCLK,
 247         0,
 248         SAR_GP_EESCLK,                  /* 0 */
 249         0,
 250         SAR_GP_EESCLK,                  /* 0 */
 251         0,
 252         SAR_GP_EESCLK,                  /* 0 */
 253         0,
 254         SAR_GP_EESCLK,                  /* 0 */
 255         0,
 256         SAR_GP_EESCLK,                  /* 0 */
 257         SAR_GP_EEDO,
 258         SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
 259         0,
 260         SAR_GP_EESCLK,                  /* 0 */
 261         SAR_GP_EEDO,
 262         SAR_GP_EESCLK | SAR_GP_EEDO     /* 1 */
 263 };
 264
 265 static u32 wrentab[] =
 266 {
 267         SAR_GP_EECS | SAR_GP_EESCLK,
 268         0,
 269         SAR_GP_EESCLK,                  /* 0 */
 270         0,
 271         SAR_GP_EESCLK,                  /* 0 */
 272         0,
 273         SAR_GP_EESCLK,                  /* 0 */
 274         0,
 275         SAR_GP_EESCLK,                  /* 0 */
 276         SAR_GP_EEDO,
 277         SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
 278         SAR_GP_EEDO,
 279         SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
 280         0,
 281         SAR_GP_EESCLK,                  /* 0 */
 282         0,
 283         SAR_GP_EESCLK                   /* 0 */
 284 };
 285
 286 static u32 rdtab[] =
 287 {
 288         SAR_GP_EECS | SAR_GP_EESCLK,
 289         0,
 290         SAR_GP_EESCLK,                  /* 0 */
 291         0,
 292         SAR_GP_EESCLK,                  /* 0 */
 293         0,
 294         SAR_GP_EESCLK,                  /* 0 */
 295         0,
 296         SAR_GP_EESCLK,                  /* 0 */
 297         0,
 298         SAR_GP_EESCLK,                  /* 0 */
 299         0,
 300         SAR_GP_EESCLK,                  /* 0 */
 301         SAR_GP_EEDO,
 302         SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
 303         SAR_GP_EEDO,
 304         SAR_GP_EESCLK | SAR_GP_EEDO     /* 1 */
 305 };
 306
 307 static u32 wrtab[] =
 308 {
 309         SAR_GP_EECS | SAR_GP_EESCLK,
 310         0,
 311         SAR_GP_EESCLK,                  /* 0 */
 312         0,
 313         SAR_GP_EESCLK,                  /* 0 */
 314         0,
 315         SAR_GP_EESCLK,                  /* 0 */
 316         0,
 317         SAR_GP_EESCLK,                  /* 0 */
 318         0,
 319         SAR_GP_EESCLK,                  /* 0 */
 320         0,
 321         SAR_GP_EESCLK,                  /* 0 */
 322         SAR_GP_EEDO,
 323         SAR_GP_EESCLK | SAR_GP_EEDO,    /* 1 */
 324         0,
 325         SAR_GP_EESCLK                   /* 0 */
 326 };
 327
 328 static u32 clktab[] =
 329 {
 330         0,
 331         SAR_GP_EESCLK,
 332         0,
 333         SAR_GP_EESCLK,
 334         0,
 335         SAR_GP_EESCLK,
 336         0,
 337         SAR_GP_EESCLK,
 338         0,
 339         SAR_GP_EESCLK,
 340         0,
 341         SAR_GP_EESCLK,
 342         0,
 343         SAR_GP_EESCLK,
 344         0,
 345         SAR_GP_EESCLK,
 346         0
 347 };
 348
 349 static u32
 350 idt77252_read_gp(struct idt77252_dev *card)
 351 {
 352         u32 gp;
 353
 354         gp = readl(SAR_REG_GP);
 355 #if 0
 356         printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
 357 #endif
 358         return gp;
 359 }
 360
 361 static void
 362 idt77252_write_gp(struct idt77252_dev *card, u32 value)
 363 {
 364         unsigned long flags;
 365
 366 #if 0
 367         printk("WR: %s %s %s\n", value & SAR_GP_EECS ? "   " : "/CS",
 368                value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
 369                value & SAR_GP_EEDO   ? "1" : "0");
 370 #endif
 371
 372         spin_lock_irqsave(&card->cmd_lock, flags);
 373         waitfor_idle(card);
 374         writel(value, SAR_REG_GP);
 375         spin_unlock_irqrestore(&card->cmd_lock, flags);
 376 }
 377
 378 static u8
 379 idt77252_eeprom_read_status(struct idt77252_dev *card)
 380 {
 381         u8 byte;
 382         u32 gp;
 383         int i, j;
 384
 385         gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
 386
 387         for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
 388                 idt77252_write_gp(card, gp | rdsrtab[i]);
 389                 udelay(5);
 390         }
 391         idt77252_write_gp(card, gp | SAR_GP_EECS);
 392         udelay(5);
 393
 394         byte = 0;
 395         for (i = 0, j = 0; i < 8; i++) {
 396                 byte <<= 1;
 397
 398                 idt77252_write_gp(card, gp | clktab[j++]);
 399                 udelay(5);
 400
 401                 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
 402
 403                 idt77252_write_gp(card, gp | clktab[j++]);
 404                 udelay(5);
 405         }
 406         idt77252_write_gp(card, gp | SAR_GP_EECS);
 407         udelay(5);
 408
 409         return byte;
 410 }
 411
 412 static u8
 413 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
 414 {
 415         u8 byte;
 416         u32 gp;
 417         int i, j;
 418
 419         gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
 420
 421         for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
 422                 idt77252_write_gp(card, gp | rdtab[i]);
 423                 udelay(5);
 424         }
 425         idt77252_write_gp(card, gp | SAR_GP_EECS);
 426         udelay(5);
 427
 428         for (i = 0, j = 0; i < 8; i++) {
 429                 idt77252_write_gp(card, gp | clktab[j++] |
 430                                         (offset & 1 ? SAR_GP_EEDO : 0));
 431                 udelay(5);
 432
 433                 idt77252_write_gp(card, gp | clktab[j++] |
 434                                         (offset & 1 ? SAR_GP_EEDO : 0));
 435                 udelay(5);
 436
 437                 offset >>= 1;
 438         }
 439         idt77252_write_gp(card, gp | SAR_GP_EECS);
 440         udelay(5);
 441
 442         byte = 0;
 443         for (i = 0, j = 0; i < 8; i++) {
 444                 byte <<= 1;
 445
 446                 idt77252_write_gp(card, gp | clktab[j++]);
 447                 udelay(5);
 448
 449                 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
 450
 451                 idt77252_write_gp(card, gp | clktab[j++]);
 452                 udelay(5);
 453         }
 454         idt77252_write_gp(card, gp | SAR_GP_EECS);
 455         udelay(5);
 456
 457         return byte;
 458 }
 459
 460 static void
 461 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
 462 {
 463         u32 gp;
 464         int i, j;
 465
 466         gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
 467
 468         for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
 469                 idt77252_write_gp(card, gp | wrentab[i]);
 470                 udelay(5);
 471         }
 472         idt77252_write_gp(card, gp | SAR_GP_EECS);
 473         udelay(5);
 474
 475         for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
 476                 idt77252_write_gp(card, gp | wrtab[i]);
 477                 udelay(5);
 478         }
 479         idt77252_write_gp(card, gp | SAR_GP_EECS);
 480         udelay(5);
 481
 482         for (i = 0, j = 0; i < 8; i++) {
 483                 idt77252_write_gp(card, gp | clktab[j++] |
 484                                         (offset & 1 ? SAR_GP_EEDO : 0));
 485                 udelay(5);
 486
 487                 idt77252_write_gp(card, gp | clktab[j++] |
 488                                         (offset & 1 ? SAR_GP_EEDO : 0));
 489                 udelay(5);
 490
 491                 offset >>= 1;
 492         }
 493         idt77252_write_gp(card, gp | SAR_GP_EECS);
 494         udelay(5);
 495
 496         for (i = 0, j = 0; i < 8; i++) {
 497                 idt77252_write_gp(card, gp | clktab[j++] |
 498                                         (data & 1 ? SAR_GP_EEDO : 0));
 499                 udelay(5);
 500
 501                 idt77252_write_gp(card, gp | clktab[j++] |
 502                                         (data & 1 ? SAR_GP_EEDO : 0));
 503                 udelay(5);
 504
 505                 data >>= 1;
 506         }
 507         idt77252_write_gp(card, gp | SAR_GP_EECS);
 508         udelay(5);
 509 }
 510
 511 static void
 512 idt77252_eeprom_init(struct idt77252_dev *card)
 513 {
 514         u32 gp;
 515
 516         gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
 517
 518         idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
 519         udelay(5);
 520         idt77252_write_gp(card, gp | SAR_GP_EECS);
 521         udelay(5);
 522         idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
 523         udelay(5);
 524         idt77252_write_gp(card, gp | SAR_GP_EECS);
 525         udelay(5);
 526 }
 527 #endif /* HAVE_EEPROM */
 528
 529
 530 #ifdef CONFIG_ATM_IDT77252_DEBUG
 531 static void
 532 dump_tct(struct idt77252_dev *card, int index)
 533 {
 534         unsigned long tct;
 535         int i;
 536
 537         tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
 538
 539         printk("%s: TCT %x:", card->name, index);
 540         for (i = 0; i < 8; i++) {
 541                 printk(" %08x", read_sram(card, tct + i));
 542         }
 543         printk("\n");
 544 }
 545
 546 static void
 547 idt77252_tx_dump(struct idt77252_dev *card)
 548 {
 549         struct atm_vcc *vcc;
 550         struct vc_map *vc;
 551         int i;
 552
 553         printk("%s\n", __func__);
 554         for (i = 0; i < card->tct_size; i++) {
 555                 vc = card->vcs[i];
 556                 if (!vc)
 557                         continue;
 558
 559                 vcc = NULL;
 560                 if (vc->rx_vcc)
 561                         vcc = vc->rx_vcc;
 562                 else if (vc->tx_vcc)
 563                         vcc = vc->tx_vcc;
 564
 565                 if (!vcc)
 566                         continue;
 567
 568                 printk("%s: Connection %d:\n", card->name, vc->index);
 569                 dump_tct(card, vc->index);
 570         }
 571 }
 572 #endif
 573
 574
 575 /*****************************************************************************/
 576 /*                                                                           */
 577 /* SCQ Handling                                                              */
 578 /*                                                                           */
 579 /*****************************************************************************/
 580
 581 static int
 582 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
 583 {
 584         struct sb_pool *pool = &card->sbpool[queue];
 585         int index;
 586
 587         index = pool->index;
 588         while (pool->skb[index]) {
 589                 index = (index + 1) & FBQ_MASK;
 590                 if (index == pool->index)
 591                         return -ENOBUFS;
 592         }
 593
 594         pool->skb[index] = skb;
 595         IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
 596
 597         pool->index = (index + 1) & FBQ_MASK;
 598         return 0;
 599 }
 600
 601 static void
 602 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
 603 {
 604         unsigned int queue, index;
 605         u32 handle;
 606
 607         handle = IDT77252_PRV_POOL(skb);
 608
 609         queue = POOL_QUEUE(handle);
 610         if (queue > 3)
 611                 return;
 612
 613         index = POOL_INDEX(handle);
 614         if (index > FBQ_SIZE - 1)
 615                 return;
 616
 617         card->sbpool[queue].skb[index] = NULL;
 618 }
 619
 620 static struct sk_buff *
 621 sb_pool_skb(struct idt77252_dev *card, u32 handle)
 622 {
 623         unsigned int queue, index;
 624
 625         queue = POOL_QUEUE(handle);
 626         if (queue > 3)
 627                 return NULL;
 628
 629         index = POOL_INDEX(handle);
 630         if (index > FBQ_SIZE - 1)
 631                 return NULL;
 632
 633         return card->sbpool[queue].skb[index];
 634 }
 635
 636 static struct scq_info *
 637 alloc_scq(struct idt77252_dev *card, int class)
 638 {
 639         struct scq_info *scq;
 640
 641         scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
 642         if (!scq)
 643                 return NULL;
 644         scq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE,
 645                                        &scq->paddr, GFP_KERNEL);
 646         if (scq->base == NULL) {
 647                 kfree(scq);
 648                 return NULL;
 649         }
 650
 651         scq->next = scq->base;
 652         scq->last = scq->base + (SCQ_ENTRIES - 1);
 653         atomic_set(&scq->used, 0);
 654
 655         spin_lock_init(&scq->lock);
 656         spin_lock_init(&scq->skblock);
 657
 658         skb_queue_head_init(&scq->transmit);
 659         skb_queue_head_init(&scq->pending);
 660
 661         TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
 662                  scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
 663
 664         return scq;
 665 }
 666
 667 static void
 668 free_scq(struct idt77252_dev *card, struct scq_info *scq)
 669 {
 670         struct sk_buff *skb;
 671         struct atm_vcc *vcc;
 672
 673         dma_free_coherent(&card->pcidev->dev, SCQ_SIZE,
 674                           scq->base, scq->paddr);
 675
 676         while ((skb = skb_dequeue(&scq->transmit))) {
 677                 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
 678                                  skb->len, DMA_TO_DEVICE);
 679
 680                 vcc = ATM_SKB(skb)->vcc;
 681                 if (vcc->pop)
 682                         vcc->pop(vcc, skb);
 683                 else
 684                         dev_kfree_skb(skb);
 685         }
 686
 687         while ((skb = skb_dequeue(&scq->pending))) {
 688                 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
 689                                  skb->len, DMA_TO_DEVICE);
 690
 691                 vcc = ATM_SKB(skb)->vcc;
 692                 if (vcc->pop)
 693                         vcc->pop(vcc, skb);
 694                 else
 695                         dev_kfree_skb(skb);
 696         }
 697
 698         kfree(scq);
 699 }
 700
 701
 702 static int
 703 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
 704 {
 705         struct scq_info *scq = vc->scq;
 706         unsigned long flags;
 707         struct scqe *tbd;
 708         int entries;
 709
 710         TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
 711
 712         atomic_inc(&scq->used);
 713         entries = atomic_read(&scq->used);
 714         if (entries > (SCQ_ENTRIES - 1)) {
 715                 atomic_dec(&scq->used);
 716                 goto out;
 717         }
 718
 719         skb_queue_tail(&scq->transmit, skb);
 720
 721         spin_lock_irqsave(&vc->lock, flags);
 722         if (vc->estimator) {
 723                 struct atm_vcc *vcc = vc->tx_vcc;
 724                 struct sock *sk = sk_atm(vcc);
 725
 726                 vc->estimator->cells += (skb->len + 47) / 48;
 727                 if (refcount_read(&sk->sk_wmem_alloc) >
 728                     (sk->sk_sndbuf >> 1)) {
 729                         u32 cps = vc->estimator->maxcps;
 730
 731                         vc->estimator->cps = cps;
 732                         vc->estimator->avcps = cps << 5;
 733                         if (vc->lacr < vc->init_er) {
 734                                 vc->lacr = vc->init_er;
 735                                 writel(TCMDQ_LACR | (vc->lacr << 16) |
 736                                        vc->index, SAR_REG_TCMDQ);
 737                         }
 738                 }
 739         }
 740         spin_unlock_irqrestore(&vc->lock, flags);
 741
 742         tbd = &IDT77252_PRV_TBD(skb);
 743
 744         spin_lock_irqsave(&scq->lock, flags);
 745         scq->next->word_1 = cpu_to_le32(tbd->word_1 |
 746                                         SAR_TBD_TSIF | SAR_TBD_GTSI);
 747         scq->next->word_2 = cpu_to_le32(tbd->word_2);
 748         scq->next->word_3 = cpu_to_le32(tbd->word_3);
 749         scq->next->word_4 = cpu_to_le32(tbd->word_4);
 750
 751         if (scq->next == scq->last)
 752                 scq->next = scq->base;
 753         else
 754                 scq->next++;
 755
 756         write_sram(card, scq->scd,
 757                    scq->paddr +
 758                    (u32)((unsigned long)scq->next - (unsigned long)scq->base));
 759         spin_unlock_irqrestore(&scq->lock, flags);
 760
 761         scq->trans_start = jiffies;
 762
 763         if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
 764                 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
 765                        SAR_REG_TCMDQ);
 766         }
 767
 768         TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
 769
 770         XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
 771                 card->name, atomic_read(&scq->used),
 772                 read_sram(card, scq->scd + 1), scq->next);
 773
 774         return 0;
 775
 776 out:
 777         if (time_after(jiffies, scq->trans_start + HZ)) {
 778                 printk("%s: Error pushing TBD for %d.%d\n",
 779                        card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
 780 #ifdef CONFIG_ATM_IDT77252_DEBUG
 781                 idt77252_tx_dump(card);
 782 #endif
 783                 scq->trans_start = jiffies;
 784         }
 785
 786         return -ENOBUFS;
 787 }
 788
 789
 790 static void
 791 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
 792 {
 793         struct scq_info *scq = vc->scq;
 794         struct sk_buff *skb;
 795         struct atm_vcc *vcc;
 796
 797         TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
 798                  card->name, atomic_read(&scq->used), scq->next);
 799
 800         skb = skb_dequeue(&scq->transmit);
 801         if (skb) {
 802                 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
 803
 804                 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
 805                                  skb->len, DMA_TO_DEVICE);
 806
 807                 vcc = ATM_SKB(skb)->vcc;
 808
 809                 if (vcc->pop)
 810                         vcc->pop(vcc, skb);
 811                 else
 812                         dev_kfree_skb(skb);
 813
 814                 atomic_inc(&vcc->stats->tx);
 815         }
 816
 817         atomic_dec(&scq->used);
 818
 819         spin_lock(&scq->skblock);
 820         while ((skb = skb_dequeue(&scq->pending))) {
 821                 if (push_on_scq(card, vc, skb)) {
 822                         skb_queue_head(&vc->scq->pending, skb);
 823                         break;
 824                 }
 825         }
 826         spin_unlock(&scq->skblock);
 827 }
 828
 829 static int
 830 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
 831           struct sk_buff *skb, int oam)
 832 {
 833         struct atm_vcc *vcc;
 834         struct scqe *tbd;
 835         unsigned long flags;
 836         int error;
 837         int aal;
 838
 839         if (skb->len == 0) {
 840                 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
 841                 return -EINVAL;
 842         }
 843
 844         TXPRINTK("%s: Sending %d bytes of data.\n",
 845                  card->name, skb->len);
 846
 847         tbd = &IDT77252_PRV_TBD(skb);
 848         vcc = ATM_SKB(skb)->vcc;
 849
 850         IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data,
 851                                                  skb->len, DMA_TO_DEVICE);
 852
 853         error = -EINVAL;
 854
 855         if (oam) {
 856                 if (skb->len != 52)
 857                         goto errout;
 858
 859                 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
 860                 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
 861                 tbd->word_3 = 0x00000000;
 862                 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
 863                               (skb->data[2] <<  8) | (skb->data[3] <<  0);
 864
 865                 if (test_bit(VCF_RSV, &vc->flags))
 866                         vc = card->vcs[0];
 867
 868                 goto done;
 869         }
 870
 871         if (test_bit(VCF_RSV, &vc->flags)) {
 872                 printk("%s: Trying to transmit on reserved VC\n", card->name);
 873                 goto errout;
 874         }
 875
 876         aal = vcc->qos.aal;
 877
 878         switch (aal) {
 879         case ATM_AAL0:
 880         case ATM_AAL34:
 881                 if (skb->len > 52)
 882                         goto errout;
 883
 884                 if (aal == ATM_AAL0)
 885                         tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
 886                                       ATM_CELL_PAYLOAD;
 887                 else
 888                         tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
 889                                       ATM_CELL_PAYLOAD;
 890
 891                 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
 892                 tbd->word_3 = 0x00000000;
 893                 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
 894                               (skb->data[2] <<  8) | (skb->data[3] <<  0);
 895                 break;
 896
 897         case ATM_AAL5:
 898                 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
 899                 tbd->word_2 = IDT77252_PRV_PADDR(skb);
 900                 tbd->word_3 = skb->len;
 901                 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
 902                               (vcc->vci << SAR_TBD_VCI_SHIFT);
 903                 break;
 904
 905         case ATM_AAL1:
 906         case ATM_AAL2:
 907         default:
 908                 printk("%s: Traffic type not supported.\n", card->name);
 909                 error = -EPROTONOSUPPORT;
 910                 goto errout;
 911         }
 912
 913 done:
 914         spin_lock_irqsave(&vc->scq->skblock, flags);
 915         skb_queue_tail(&vc->scq->pending, skb);
 916
 917         while ((skb = skb_dequeue(&vc->scq->pending))) {
 918                 if (push_on_scq(card, vc, skb)) {
 919                         skb_queue_head(&vc->scq->pending, skb);
 920                         break;
 921                 }
 922         }
 923         spin_unlock_irqrestore(&vc->scq->skblock, flags);
 924
 925         return 0;
 926
 927 errout:
 928         dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
 929                          skb->len, DMA_TO_DEVICE);
 930         return error;
 931 }
 932
 933 static unsigned long
 934 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
 935 {
 936         int i;
 937
 938         for (i = 0; i < card->scd_size; i++) {
 939                 if (!card->scd2vc[i]) {
 940                         card->scd2vc[i] = vc;
 941                         vc->scd_index = i;
 942                         return card->scd_base + i * SAR_SRAM_SCD_SIZE;
 943                 }
 944         }
 945         return 0;
 946 }
 947
 948 static void
 949 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
 950 {
 951         write_sram(card, scq->scd, scq->paddr);
 952         write_sram(card, scq->scd + 1, 0x00000000);
 953         write_sram(card, scq->scd + 2, 0xffffffff);
 954         write_sram(card, scq->scd + 3, 0x00000000);
 955 }
 956
 957 static void
 958 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
 959 {
 960         return;
 961 }
 962
 963 /*****************************************************************************/
 964 /*                                                                           */
 965 /* RSQ Handling                                                              */
 966 /*                                                                           */
 967 /*****************************************************************************/
 968
 969 static int
 970 init_rsq(struct idt77252_dev *card)
 971 {
 972         struct rsq_entry *rsqe;
 973
 974         card->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
 975                                             &card->rsq.paddr, GFP_KERNEL);
 976         if (card->rsq.base == NULL) {
 977                 printk("%s: can't allocate RSQ.\n", card->name);
 978                 return -1;
 979         }
 980
 981         card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
 982         card->rsq.next = card->rsq.last;
 983         for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
 984                 rsqe->word_4 = 0;
 985
 986         writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
 987                SAR_REG_RSQH);
 988         writel(card->rsq.paddr, SAR_REG_RSQB);
 989
 990         IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
 991                 (unsigned long) card->rsq.base,
 992                 readl(SAR_REG_RSQB));
 993         IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
 994                 card->name,
 995                 readl(SAR_REG_RSQH),
 996                 readl(SAR_REG_RSQB),
 997                 readl(SAR_REG_RSQT));
 998
 999         return 0;
1000 }
1001
1002 static void
1003 deinit_rsq(struct idt77252_dev *card)
1004 {
1005         dma_free_coherent(&card->pcidev->dev, RSQSIZE,
1006                           card->rsq.base, card->rsq.paddr);
1007 }
1008
1009 static void
1010 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1011 {
1012         struct atm_vcc *vcc;
1013         struct sk_buff *skb;
1014         struct rx_pool *rpp;
1015         struct vc_map *vc;
1016         u32 header, vpi, vci;
1017         u32 stat;
1018         int i;
1019
1020         stat = le32_to_cpu(rsqe->word_4);
1021
1022         if (stat & SAR_RSQE_IDLE) {
1023                 RXPRINTK("%s: message about inactive connection.\n",
1024                          card->name);
1025                 return;
1026         }
1027
1028         skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1029         if (skb == NULL) {
1030                 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1031                        card->name, __func__,
1032                        le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1033                        le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1034                 return;
1035         }
1036
1037         header = le32_to_cpu(rsqe->word_1);
1038         vpi = (header >> 16) & 0x00ff;
1039         vci = (header >>  0) & 0xffff;
1040
1041         RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1042                  card->name, vpi, vci, skb, skb->data);
1043
1044         if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1045                 printk("%s: SDU received for out-of-range vc %u.%u\n",
1046                        card->name, vpi, vci);
1047                 recycle_rx_skb(card, skb);
1048                 return;
1049         }
1050
1051         vc = card->vcs[VPCI2VC(card, vpi, vci)];
1052         if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1053                 printk("%s: SDU received on non RX vc %u.%u\n",
1054                        card->name, vpi, vci);
1055                 recycle_rx_skb(card, skb);
1056                 return;
1057         }
1058
1059         vcc = vc->rx_vcc;
1060
1061         dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1062                                 skb_end_pointer(skb) - skb->data,
1063                                 DMA_FROM_DEVICE);
1064
1065         if ((vcc->qos.aal == ATM_AAL0) ||
1066             (vcc->qos.aal == ATM_AAL34)) {
1067                 struct sk_buff *sb;
1068                 unsigned char *cell;
1069                 u32 aal0;
1070
1071                 cell = skb->data;
1072                 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1073                         if ((sb = dev_alloc_skb(64)) == NULL) {
1074                                 printk("%s: Can't allocate buffers for aal0.\n",
1075                                        card->name);
1076                                 atomic_add(i, &vcc->stats->rx_drop);
1077                                 break;
1078                         }
1079                         if (!atm_charge(vcc, sb->truesize)) {
1080                                 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1081                                          card->name);
1082                                 atomic_add(i - 1, &vcc->stats->rx_drop);
1083                                 dev_kfree_skb(sb);
1084                                 break;
1085                         }
1086                         aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1087                                (vci << ATM_HDR_VCI_SHIFT);
1088                         aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1089                         aal0 |= (stat & SAR_RSQE_CLP)  ? 0x00000001 : 0;
1090
1091                         *((u32 *) sb->data) = aal0;
1092                         skb_put(sb, sizeof(u32));
1093                         skb_put_data(sb, cell, ATM_CELL_PAYLOAD);
1094
1095                         ATM_SKB(sb)->vcc = vcc;
1096                         __net_timestamp(sb);
1097                         vcc->push(vcc, sb);
1098                         atomic_inc(&vcc->stats->rx);
1099
1100                         cell += ATM_CELL_PAYLOAD;
1101                 }
1102
1103                 recycle_rx_skb(card, skb);
1104                 return;
1105         }
1106         if (vcc->qos.aal != ATM_AAL5) {
1107                 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1108                        card->name, vcc->qos.aal);
1109                 recycle_rx_skb(card, skb);
1110                 return;
1111         }
1112         skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1113
1114         rpp = &vc->rcv.rx_pool;
1115
1116         __skb_queue_tail(&rpp->queue, skb);
1117         rpp->len += skb->len;
1118
1119         if (stat & SAR_RSQE_EPDU) {
1120                 unsigned char *l1l2;
1121                 unsigned int len;
1122
1123                 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1124
1125                 len = (l1l2[0] << 8) | l1l2[1];
1126                 len = len ? len : 0x10000;
1127
1128                 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1129
1130                 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1131                         RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1132                                  "(CDC: %08x)\n",
1133                                  card->name, len, rpp->len, readl(SAR_REG_CDC));
1134                         recycle_rx_pool_skb(card, rpp);
1135                         atomic_inc(&vcc->stats->rx_err);
1136                         return;
1137                 }
1138                 if (stat & SAR_RSQE_CRC) {
1139                         RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1140                         recycle_rx_pool_skb(card, rpp);
1141                         atomic_inc(&vcc->stats->rx_err);
1142                         return;
1143                 }
1144                 if (skb_queue_len(&rpp->queue) > 1) {
1145                         struct sk_buff *sb;
1146
1147                         skb = dev_alloc_skb(rpp->len);
1148                         if (!skb) {
1149                                 RXPRINTK("%s: Can't alloc RX skb.\n",
1150                                          card->name);
1151                                 recycle_rx_pool_skb(card, rpp);
1152                                 atomic_inc(&vcc->stats->rx_err);
1153                                 return;
1154                         }
1155                         if (!atm_charge(vcc, skb->truesize)) {
1156                                 recycle_rx_pool_skb(card, rpp);
1157                                 dev_kfree_skb(skb);
1158                                 return;
1159                         }
1160                         skb_queue_walk(&rpp->queue, sb)
1161                                 skb_put_data(skb, sb->data, sb->len);
1162
1163                         recycle_rx_pool_skb(card, rpp);
1164
1165                         skb_trim(skb, len);
1166                         ATM_SKB(skb)->vcc = vcc;
1167                         __net_timestamp(skb);
1168
1169                         vcc->push(vcc, skb);
1170                         atomic_inc(&vcc->stats->rx);
1171
1172                         return;
1173                 }
1174
1175                 flush_rx_pool(card, rpp);
1176
1177                 if (!atm_charge(vcc, skb->truesize)) {
1178                         recycle_rx_skb(card, skb);
1179                         return;
1180                 }
1181
1182                 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1183                                  skb_end_pointer(skb) - skb->data,
1184                                  DMA_FROM_DEVICE);
1185                 sb_pool_remove(card, skb);
1186
1187                 skb_trim(skb, len);
1188                 ATM_SKB(skb)->vcc = vcc;
1189                 __net_timestamp(skb);
1190
1191                 vcc->push(vcc, skb);
1192                 atomic_inc(&vcc->stats->rx);
1193
1194                 if (skb->truesize > SAR_FB_SIZE_3)
1195                         add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1196                 else if (skb->truesize > SAR_FB_SIZE_2)
1197                         add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1198                 else if (skb->truesize > SAR_FB_SIZE_1)
1199                         add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1200                 else
1201                         add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1202                 return;
1203         }
1204 }
1205
1206 static void
1207 idt77252_rx(struct idt77252_dev *card)
1208 {
1209         struct rsq_entry *rsqe;
1210
1211         if (card->rsq.next == card->rsq.last)
1212                 rsqe = card->rsq.base;
1213         else
1214                 rsqe = card->rsq.next + 1;
1215
1216         if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1217                 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1218                 return;
1219         }
1220
1221         do {
1222                 dequeue_rx(card, rsqe);
1223                 rsqe->word_4 = 0;
1224                 card->rsq.next = rsqe;
1225                 if (card->rsq.next == card->rsq.last)
1226                         rsqe = card->rsq.base;
1227                 else
1228                         rsqe = card->rsq.next + 1;
1229         } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1230
1231         writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1232                SAR_REG_RSQH);
1233 }
1234
1235 static void
1236 idt77252_rx_raw(struct idt77252_dev *card)
1237 {
1238         struct sk_buff  *queue;
1239         u32             head, tail;
1240         struct atm_vcc  *vcc;
1241         struct vc_map   *vc;
1242         struct sk_buff  *sb;
1243
1244         if (card->raw_cell_head == NULL) {
1245                 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1246                 card->raw_cell_head = sb_pool_skb(card, handle);
1247         }
1248
1249         queue = card->raw_cell_head;
1250         if (!queue)
1251                 return;
1252
1253         head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1254         tail = readl(SAR_REG_RAWCT);
1255
1256         dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue),
1257                                 skb_end_offset(queue) - 16,
1258                                 DMA_FROM_DEVICE);
1259
1260         while (head != tail) {
1261                 unsigned int vpi, vci;
1262                 u32 header;
1263
1264                 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1265
1266                 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1267                 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1268
1269 #ifdef CONFIG_ATM_IDT77252_DEBUG
1270                 if (debug & DBG_RAW_CELL) {
1271                         int i;
1272
1273                         printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1274                                card->name, (header >> 28) & 0x000f,
1275                                (header >> 20) & 0x00ff,
1276                                (header >>  4) & 0xffff,
1277                                (header >>  1) & 0x0007,
1278                                (header >>  0) & 0x0001);
1279                         for (i = 16; i < 64; i++)
1280                                 printk(" %02x", queue->data[i]);
1281                         printk("\n");
1282                 }
1283 #endif
1284
1285                 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1286                         RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1287                                 card->name, vpi, vci);
1288                         goto drop;
1289                 }
1290
1291                 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1292                 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1293                         RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1294                                 card->name, vpi, vci);
1295                         goto drop;
1296                 }
1297
1298                 vcc = vc->rx_vcc;
1299
1300                 if (vcc->qos.aal != ATM_AAL0) {
1301                         RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1302                                 card->name, vpi, vci);
1303                         atomic_inc(&vcc->stats->rx_drop);
1304                         goto drop;
1305                 }
1306
1307                 if ((sb = dev_alloc_skb(64)) == NULL) {
1308                         printk("%s: Can't allocate buffers for AAL0.\n",
1309                                card->name);
1310                         atomic_inc(&vcc->stats->rx_err);
1311                         goto drop;
1312                 }
1313
1314                 if (!atm_charge(vcc, sb->truesize)) {
1315                         RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1316                                  card->name);
1317                         dev_kfree_skb(sb);
1318                         goto drop;
1319                 }
1320
1321                 *((u32 *) sb->data) = header;
1322                 skb_put(sb, sizeof(u32));
1323                 skb_put_data(sb, &(queue->data[16]), ATM_CELL_PAYLOAD);
1324
1325                 ATM_SKB(sb)->vcc = vcc;
1326                 __net_timestamp(sb);
1327                 vcc->push(vcc, sb);
1328                 atomic_inc(&vcc->stats->rx);
1329
1330 drop:
1331                 skb_pull(queue, 64);
1332
1333                 head = IDT77252_PRV_PADDR(queue)
1334                                         + (queue->data - queue->head - 16);
1335
1336                 if (queue->len < 128) {
1337                         struct sk_buff *next;
1338                         u32 handle;
1339
1340                         head = le32_to_cpu(*(u32 *) &queue->data[0]);
1341                         handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1342
1343                         next = sb_pool_skb(card, handle);
1344                         recycle_rx_skb(card, queue);
1345
1346                         if (next) {
1347                                 card->raw_cell_head = next;
1348                                 queue = card->raw_cell_head;
1349                                 dma_sync_single_for_cpu(&card->pcidev->dev,
1350                                                         IDT77252_PRV_PADDR(queue),
1351                                                         (skb_end_pointer(queue) -
1352                                                          queue->data),
1353                                                         DMA_FROM_DEVICE);
1354                         } else {
1355                                 card->raw_cell_head = NULL;
1356                                 printk("%s: raw cell queue overrun\n",
1357                                        card->name);
1358                                 break;
1359                         }
1360                 }
1361         }
1362 }
1363
1364
1365 /*****************************************************************************/
1366 /*                                                                           */
1367 /* TSQ Handling                                                              */
1368 /*                                                                           */
1369 /*****************************************************************************/
1370
1371 static int
1372 init_tsq(struct idt77252_dev *card)
1373 {
1374         struct tsq_entry *tsqe;
1375
1376         card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
1377                                             &card->tsq.paddr, GFP_KERNEL);
1378         if (card->tsq.base == NULL) {
1379                 printk("%s: can't allocate TSQ.\n", card->name);
1380                 return -1;
1381         }
1382
1383         card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1384         card->tsq.next = card->tsq.last;
1385         for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1386                 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1387
1388         writel(card->tsq.paddr, SAR_REG_TSQB);
1389         writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1390                SAR_REG_TSQH);
1391
1392         return 0;
1393 }
1394
1395 static void
1396 deinit_tsq(struct idt77252_dev *card)
1397 {
1398         dma_free_coherent(&card->pcidev->dev, TSQSIZE,
1399                           card->tsq.base, card->tsq.paddr);
1400 }
1401
1402 static void
1403 idt77252_tx(struct idt77252_dev *card)
1404 {
1405         struct tsq_entry *tsqe;
1406         unsigned int vpi, vci;
1407         struct vc_map *vc;
1408         u32 conn, stat;
1409
1410         if (card->tsq.next == card->tsq.last)
1411                 tsqe = card->tsq.base;
1412         else
1413                 tsqe = card->tsq.next + 1;
1414
1415         TXPRINTK("idt77252_tx: tsq  %p: base %p, next %p, last %p\n", tsqe,
1416                  card->tsq.base, card->tsq.next, card->tsq.last);
1417         TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1418                  readl(SAR_REG_TSQB),
1419                  readl(SAR_REG_TSQT),
1420                  readl(SAR_REG_TSQH));
1421
1422         stat = le32_to_cpu(tsqe->word_2);
1423
1424         if (stat & SAR_TSQE_INVALID)
1425                 return;
1426
1427         do {
1428                 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1429                          le32_to_cpu(tsqe->word_1),
1430                          le32_to_cpu(tsqe->word_2));
1431
1432                 switch (stat & SAR_TSQE_TYPE) {
1433                 case SAR_TSQE_TYPE_TIMER:
1434                         TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1435                         break;
1436
1437                 case SAR_TSQE_TYPE_IDLE:
1438
1439                         conn = le32_to_cpu(tsqe->word_1);
1440
1441                         if (SAR_TSQE_TAG(stat) == 0x10) {
1442 #ifdef  NOTDEF
1443                                 printk("%s: Connection %d halted.\n",
1444                                        card->name,
1445                                        le32_to_cpu(tsqe->word_1) & 0x1fff);
1446 #endif
1447                                 break;
1448                         }
1449
1450                         vc = card->vcs[conn & 0x1fff];
1451                         if (!vc) {
1452                                 printk("%s: could not find VC from conn %d\n",
1453                                        card->name, conn & 0x1fff);
1454                                 break;
1455                         }
1456
1457                         printk("%s: Connection %d IDLE.\n",
1458                                card->name, vc->index);
1459
1460                         set_bit(VCF_IDLE, &vc->flags);
1461                         break;
1462
1463                 case SAR_TSQE_TYPE_TSR:
1464
1465                         conn = le32_to_cpu(tsqe->word_1);
1466
1467                         vc = card->vcs[conn & 0x1fff];
1468                         if (!vc) {
1469                                 printk("%s: no VC at index %d\n",
1470                                        card->name,
1471                                        le32_to_cpu(tsqe->word_1) & 0x1fff);
1472                                 break;
1473                         }
1474
1475                         drain_scq(card, vc);
1476                         break;
1477
1478                 case SAR_TSQE_TYPE_TBD_COMP:
1479
1480                         conn = le32_to_cpu(tsqe->word_1);
1481
1482                         vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1483                         vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1484
1485                         if (vpi >= (1 << card->vpibits) ||
1486                             vci >= (1 << card->vcibits)) {
1487                                 printk("%s: TBD complete: "
1488                                        "out of range VPI.VCI %u.%u\n",
1489                                        card->name, vpi, vci);
1490                                 break;
1491                         }
1492
1493                         vc = card->vcs[VPCI2VC(card, vpi, vci)];
1494                         if (!vc) {
1495                                 printk("%s: TBD complete: "
1496                                        "no VC at VPI.VCI %u.%u\n",
1497                                        card->name, vpi, vci);
1498                                 break;
1499                         }
1500
1501                         drain_scq(card, vc);
1502                         break;
1503                 }
1504
1505                 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1506
1507                 card->tsq.next = tsqe;
1508                 if (card->tsq.next == card->tsq.last)
1509                         tsqe = card->tsq.base;
1510                 else
1511                         tsqe = card->tsq.next + 1;
1512
1513                 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1514                          card->tsq.base, card->tsq.next, card->tsq.last);
1515
1516                 stat = le32_to_cpu(tsqe->word_2);
1517
1518         } while (!(stat & SAR_TSQE_INVALID));
1519
1520         writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1521                SAR_REG_TSQH);
1522
1523         XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1524                 card->index, readl(SAR_REG_TSQH),
1525                 readl(SAR_REG_TSQT), card->tsq.next);
1526 }
1527
1528
1529 static void
1530 tst_timer(struct timer_list *t)
1531 {
1532         struct idt77252_dev *card = from_timer(card, t, tst_timer);
1533         unsigned long base, idle, jump;
1534         unsigned long flags;
1535         u32 pc;
1536         int e;
1537
1538         spin_lock_irqsave(&card->tst_lock, flags);
1539
1540         base = card->tst[card->tst_index];
1541         idle = card->tst[card->tst_index ^ 1];
1542
1543         if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1544                 jump = base + card->tst_size - 2;
1545
1546                 pc = readl(SAR_REG_NOW) >> 2;
1547                 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1548                         mod_timer(&card->tst_timer, jiffies + 1);
1549                         goto out;
1550                 }
1551
1552                 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1553
1554                 card->tst_index ^= 1;
1555                 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1556
1557                 base = card->tst[card->tst_index];
1558                 idle = card->tst[card->tst_index ^ 1];
1559
1560                 for (e = 0; e < card->tst_size - 2; e++) {
1561                         if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1562                                 write_sram(card, idle + e,
1563                                            card->soft_tst[e].tste & TSTE_MASK);
1564                                 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1565                         }
1566                 }
1567         }
1568
1569         if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1570
1571                 for (e = 0; e < card->tst_size - 2; e++) {
1572                         if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1573                                 write_sram(card, idle + e,
1574                                            card->soft_tst[e].tste & TSTE_MASK);
1575                                 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1576                                 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1577                         }
1578                 }
1579
1580                 jump = base + card->tst_size - 2;
1581
1582                 write_sram(card, jump, TSTE_OPC_NULL);
1583                 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1584
1585                 mod_timer(&card->tst_timer, jiffies + 1);
1586         }
1587
1588 out:
1589         spin_unlock_irqrestore(&card->tst_lock, flags);
1590 }
1591
1592 static int
1593 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1594            int n, unsigned int opc)
1595 {
1596         unsigned long cl, avail;
1597         unsigned long idle;
1598         int e, r;
1599         u32 data;
1600
1601         avail = card->tst_size - 2;
1602         for (e = 0; e < avail; e++) {
1603                 if (card->soft_tst[e].vc == NULL)
1604                         break;
1605         }
1606         if (e >= avail) {
1607                 printk("%s: No free TST entries found\n", card->name);
1608                 return -1;
1609         }
1610
1611         NPRINTK("%s: conn %d: first TST entry at %d.\n",
1612                 card->name, vc ? vc->index : -1, e);
1613
1614         r = n;
1615         cl = avail;
1616         data = opc & TSTE_OPC_MASK;
1617         if (vc && (opc != TSTE_OPC_NULL))
1618                 data = opc | vc->index;
1619
1620         idle = card->tst[card->tst_index ^ 1];
1621
1622         /*
1623          * Fill Soft TST.
1624          */
1625         while (r > 0) {
1626                 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1627                         if (vc)
1628                                 card->soft_tst[e].vc = vc;
1629                         else
1630                                 card->soft_tst[e].vc = (void *)-1;
1631
1632                         card->soft_tst[e].tste = data;
1633                         if (timer_pending(&card->tst_timer))
1634                                 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1635                         else {
1636                                 write_sram(card, idle + e, data);
1637                                 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1638                         }
1639
1640                         cl -= card->tst_size;
1641                         r--;
1642                 }
1643
1644                 if (++e == avail)
1645                         e = 0;
1646                 cl += n;
1647         }
1648
1649         return 0;
1650 }
1651
1652 static int
1653 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1654 {
1655         unsigned long flags;
1656         int res;
1657
1658         spin_lock_irqsave(&card->tst_lock, flags);
1659
1660         res = __fill_tst(card, vc, n, opc);
1661
1662         set_bit(TST_SWITCH_PENDING, &card->tst_state);
1663         if (!timer_pending(&card->tst_timer))
1664                 mod_timer(&card->tst_timer, jiffies + 1);
1665
1666         spin_unlock_irqrestore(&card->tst_lock, flags);
1667         return res;
1668 }
1669
1670 static int
1671 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1672 {
1673         unsigned long idle;
1674         int e;
1675
1676         idle = card->tst[card->tst_index ^ 1];
1677
1678         for (e = 0; e < card->tst_size - 2; e++) {
1679                 if (card->soft_tst[e].vc == vc) {
1680                         card->soft_tst[e].vc = NULL;
1681
1682                         card->soft_tst[e].tste = TSTE_OPC_VAR;
1683                         if (timer_pending(&card->tst_timer))
1684                                 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1685                         else {
1686                                 write_sram(card, idle + e, TSTE_OPC_VAR);
1687                                 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1688                         }
1689                 }
1690         }
1691
1692         return 0;
1693 }
1694
1695 static int
1696 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1697 {
1698         unsigned long flags;
1699         int res;
1700
1701         spin_lock_irqsave(&card->tst_lock, flags);
1702
1703         res = __clear_tst(card, vc);
1704
1705         set_bit(TST_SWITCH_PENDING, &card->tst_state);
1706         if (!timer_pending(&card->tst_timer))
1707                 mod_timer(&card->tst_timer, jiffies + 1);
1708
1709         spin_unlock_irqrestore(&card->tst_lock, flags);
1710         return res;
1711 }
1712
1713 static int
1714 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1715            int n, unsigned int opc)
1716 {
1717         unsigned long flags;
1718         int res;
1719
1720         spin_lock_irqsave(&card->tst_lock, flags);
1721
1722         __clear_tst(card, vc);
1723         res = __fill_tst(card, vc, n, opc);
1724
1725         set_bit(TST_SWITCH_PENDING, &card->tst_state);
1726         if (!timer_pending(&card->tst_timer))
1727                 mod_timer(&card->tst_timer, jiffies + 1);
1728
1729         spin_unlock_irqrestore(&card->tst_lock, flags);
1730         return res;
1731 }
1732
1733
1734 static int
1735 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1736 {
1737         unsigned long tct;
1738
1739         tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1740
1741         switch (vc->class) {
1742         case SCHED_CBR:
1743                 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1744                         card->name, tct, vc->scq->scd);
1745
1746                 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1747                 write_sram(card, tct + 1, 0);
1748                 write_sram(card, tct + 2, 0);
1749                 write_sram(card, tct + 3, 0);
1750                 write_sram(card, tct + 4, 0);
1751                 write_sram(card, tct + 5, 0);
1752                 write_sram(card, tct + 6, 0);
1753                 write_sram(card, tct + 7, 0);
1754                 break;
1755
1756         case SCHED_UBR:
1757                 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1758                         card->name, tct, vc->scq->scd);
1759
1760                 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1761                 write_sram(card, tct + 1, 0);
1762                 write_sram(card, tct + 2, TCT_TSIF);
1763                 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1764                 write_sram(card, tct + 4, 0);
1765                 write_sram(card, tct + 5, vc->init_er);
1766                 write_sram(card, tct + 6, 0);
1767                 write_sram(card, tct + 7, TCT_FLAG_UBR);
1768                 break;
1769
1770         case SCHED_VBR:
1771         case SCHED_ABR:
1772         default:
1773                 return -ENOSYS;
1774         }
1775
1776         return 0;
1777 }
1778
1779 /*****************************************************************************/
1780 /*                                                                           */
1781 /* FBQ Handling                                                              */
1782 /*                                                                           */
1783 /*****************************************************************************/
1784
1785 static __inline__ int
1786 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1787 {
1788         return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1789 }
1790
1791 static __inline__ int
1792 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1793 {
1794         return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1795 }
1796
1797 static int
1798 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1799 {
1800         unsigned long flags;
1801         u32 handle;
1802         u32 addr;
1803
1804         skb->data = skb->head;
1805         skb_reset_tail_pointer(skb);
1806         skb->len = 0;
1807
1808         skb_reserve(skb, 16);
1809
1810         switch (queue) {
1811         case 0:
1812                 skb_put(skb, SAR_FB_SIZE_0);
1813                 break;
1814         case 1:
1815                 skb_put(skb, SAR_FB_SIZE_1);
1816                 break;
1817         case 2:
1818                 skb_put(skb, SAR_FB_SIZE_2);
1819                 break;
1820         case 3:
1821                 skb_put(skb, SAR_FB_SIZE_3);
1822                 break;
1823         default:
1824                 return -1;
1825         }
1826
1827         if (idt77252_fbq_full(card, queue))
1828                 return -1;
1829
1830         memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1831
1832         handle = IDT77252_PRV_POOL(skb);
1833         addr = IDT77252_PRV_PADDR(skb);
1834
1835         spin_lock_irqsave(&card->cmd_lock, flags);
1836         writel(handle, card->fbq[queue]);
1837         writel(addr, card->fbq[queue]);
1838         spin_unlock_irqrestore(&card->cmd_lock, flags);
1839
1840         return 0;
1841 }
1842
1843 static void
1844 add_rx_skb(struct idt77252_dev *card, int queue,
1845            unsigned int size, unsigned int count)
1846 {
1847         struct sk_buff *skb;
1848         dma_addr_t paddr;
1849         u32 handle;
1850
1851         while (count--) {
1852                 skb = dev_alloc_skb(size);
1853                 if (!skb)
1854                         return;
1855
1856                 if (sb_pool_add(card, skb, queue)) {
1857                         printk("%s: SB POOL full\n", __func__);
1858                         goto outfree;
1859                 }
1860
1861                 paddr = dma_map_single(&card->pcidev->dev, skb->data,
1862                                        skb_end_pointer(skb) - skb->data,
1863                                        DMA_FROM_DEVICE);
1864                 IDT77252_PRV_PADDR(skb) = paddr;
1865
1866                 if (push_rx_skb(card, skb, queue)) {
1867                         printk("%s: FB QUEUE full\n", __func__);
1868                         goto outunmap;
1869                 }
1870         }
1871
1872         return;
1873
1874 outunmap:
1875         dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1876                          skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
1877
1878         handle = IDT77252_PRV_POOL(skb);
1879         card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1880
1881 outfree:
1882         dev_kfree_skb(skb);
1883 }
1884
1885
1886 static void
1887 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1888 {
1889         u32 handle = IDT77252_PRV_POOL(skb);
1890         int err;
1891
1892         dma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1893                                    skb_end_pointer(skb) - skb->data,
1894                                    DMA_FROM_DEVICE);
1895
1896         err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1897         if (err) {
1898                 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
1899                                  skb_end_pointer(skb) - skb->data,
1900                                  DMA_FROM_DEVICE);
1901                 sb_pool_remove(card, skb);
1902                 dev_kfree_skb(skb);
1903         }
1904 }
1905
1906 static void
1907 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1908 {
1909         skb_queue_head_init(&rpp->queue);
1910         rpp->len = 0;
1911 }
1912
1913 static void
1914 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1915 {
1916         struct sk_buff *skb, *tmp;
1917
1918         skb_queue_walk_safe(&rpp->queue, skb, tmp)
1919                 recycle_rx_skb(card, skb);
1920
1921         flush_rx_pool(card, rpp);
1922 }
1923
1924 /*****************************************************************************/
1925 /*                                                                           */
1926 /* ATM Interface                                                             */
1927 /*                                                                           */
1928 /*****************************************************************************/
1929
1930 static void
1931 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1932 {
1933         write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1934 }
1935
1936 static unsigned char
1937 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1938 {
1939         return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1940 }
1941
1942 static inline int
1943 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1944 {
1945         struct atm_dev *dev = vcc->dev;
1946         struct idt77252_dev *card = dev->dev_data;
1947         struct vc_map *vc = vcc->dev_data;
1948         int err;
1949
1950         if (vc == NULL) {
1951                 printk("%s: NULL connection in send().\n", card->name);
1952                 atomic_inc(&vcc->stats->tx_err);
1953                 dev_kfree_skb(skb);
1954                 return -EINVAL;
1955         }
1956         if (!test_bit(VCF_TX, &vc->flags)) {
1957                 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1958                 atomic_inc(&vcc->stats->tx_err);
1959                 dev_kfree_skb(skb);
1960                 return -EINVAL;
1961         }
1962
1963         switch (vcc->qos.aal) {
1964         case ATM_AAL0:
1965         case ATM_AAL1:
1966         case ATM_AAL5:
1967                 break;
1968         default:
1969                 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1970                 atomic_inc(&vcc->stats->tx_err);
1971                 dev_kfree_skb(skb);
1972                 return -EINVAL;
1973         }
1974
1975         if (skb_shinfo(skb)->nr_frags != 0) {
1976                 printk("%s: No scatter-gather yet.\n", card->name);
1977                 atomic_inc(&vcc->stats->tx_err);
1978                 dev_kfree_skb(skb);
1979                 return -EINVAL;
1980         }
1981         ATM_SKB(skb)->vcc = vcc;
1982
1983         err = queue_skb(card, vc, skb, oam);
1984         if (err) {
1985                 atomic_inc(&vcc->stats->tx_err);
1986                 dev_kfree_skb(skb);
1987                 return err;
1988         }
1989
1990         return 0;
1991 }
1992
1993 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
1994 {
1995         return idt77252_send_skb(vcc, skb, 0);
1996 }
1997
1998 static int
1999 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2000 {
2001         struct atm_dev *dev = vcc->dev;
2002         struct idt77252_dev *card = dev->dev_data;
2003         struct sk_buff *skb;
2004
2005         skb = dev_alloc_skb(64);
2006         if (!skb) {
2007                 printk("%s: Out of memory in send_oam().\n", card->name);
2008                 atomic_inc(&vcc->stats->tx_err);
2009                 return -ENOMEM;
2010         }
2011         refcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2012
2013         skb_put_data(skb, cell, 52);
2014
2015         return idt77252_send_skb(vcc, skb, 1);
2016 }
2017
2018 static __inline__ unsigned int
2019 idt77252_fls(unsigned int x)
2020 {
2021         int r = 1;
2022
2023         if (x == 0)
2024                 return 0;
2025         if (x & 0xffff0000) {
2026                 x >>= 16;
2027                 r += 16;
2028         }
2029         if (x & 0xff00) {
2030                 x >>= 8;
2031                 r += 8;
2032         }
2033         if (x & 0xf0) {
2034                 x >>= 4;
2035                 r += 4;
2036         }
2037         if (x & 0xc) {
2038                 x >>= 2;
2039                 r += 2;
2040         }
2041         if (x & 0x2)
2042                 r += 1;
2043         return r;
2044 }
2045
2046 static u16
2047 idt77252_int_to_atmfp(unsigned int rate)
2048 {
2049         u16 m, e;
2050
2051         if (rate == 0)
2052                 return 0;
2053         e = idt77252_fls(rate) - 1;
2054         if (e < 9)
2055                 m = (rate - (1 << e)) << (9 - e);
2056         else if (e == 9)
2057                 m = (rate - (1 << e));
2058         else /* e > 9 */
2059                 m = (rate - (1 << e)) >> (e - 9);
2060         return 0x4000 | (e << 9) | m;
2061 }
2062
2063 static u8
2064 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2065 {
2066         u16 afp;
2067
2068         afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2069         if (pcr < 0)
2070                 return rate_to_log[(afp >> 5) & 0x1ff];
2071         return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2072 }
2073
2074 static void
2075 idt77252_est_timer(struct timer_list *t)
2076 {
2077         struct rate_estimator *est = from_timer(est, t, timer);
2078         struct vc_map *vc = est->vc;
2079         struct idt77252_dev *card = vc->card;
2080         unsigned long flags;
2081         u32 rate, cps;
2082         u64 ncells;
2083         u8 lacr;
2084
2085         spin_lock_irqsave(&vc->lock, flags);
2086         if (!vc->estimator)
2087                 goto out;
2088         ncells = est->cells;
2089
2090         rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2091         est->last_cells = ncells;
2092         est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2093         est->cps = (est->avcps + 0x1f) >> 5;
2094
2095         cps = est->cps;
2096         if (cps < (est->maxcps >> 4))
2097                 cps = est->maxcps >> 4;
2098
2099         lacr = idt77252_rate_logindex(card, cps);
2100         if (lacr > vc->max_er)
2101                 lacr = vc->max_er;
2102
2103         if (lacr != vc->lacr) {
2104                 vc->lacr = lacr;
2105                 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2106         }
2107
2108         est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2109         add_timer(&est->timer);
2110
2111 out:
2112         spin_unlock_irqrestore(&vc->lock, flags);
2113 }
2114
2115 static struct rate_estimator *
2116 idt77252_init_est(struct vc_map *vc, int pcr)
2117 {
2118         struct rate_estimator *est;
2119
2120         est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2121         if (!est)
2122                 return NULL;
2123         est->maxcps = pcr < 0 ? -pcr : pcr;
2124         est->cps = est->maxcps;
2125         est->avcps = est->cps << 5;
2126         est->vc = vc;
2127
2128         est->interval = 2;              /* XXX: make this configurable */
2129         est->ewma_log = 2;              /* XXX: make this configurable */
2130         timer_setup(&est->timer, idt77252_est_timer, 0);
2131         mod_timer(&est->timer, jiffies + ((HZ / 4) << est->interval));
2132
2133         return est;
2134 }
2135
2136 static int
2137 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2138                   struct atm_vcc *vcc, struct atm_qos *qos)
2139 {
2140         int tst_free, tst_used, tst_entries;
2141         unsigned long tmpl, modl;
2142         int tcr, tcra;
2143
2144         if ((qos->txtp.max_pcr == 0) &&
2145             (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2146                 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2147                        card->name);
2148                 return -EINVAL;
2149         }
2150
2151         tst_used = 0;
2152         tst_free = card->tst_free;
2153         if (test_bit(VCF_TX, &vc->flags))
2154                 tst_used = vc->ntste;
2155         tst_free += tst_used;
2156
2157         tcr = atm_pcr_goal(&qos->txtp);
2158         tcra = tcr >= 0 ? tcr : -tcr;
2159
2160         TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2161
2162         tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2163         modl = tmpl % (unsigned long)card->utopia_pcr;
2164
2165         tst_entries = (int) (tmpl / card->utopia_pcr);
2166         if (tcr > 0) {
2167                 if (modl > 0)
2168                         tst_entries++;
2169         } else if (tcr == 0) {
2170                 tst_entries = tst_free - SAR_TST_RESERVED;
2171                 if (tst_entries <= 0) {
2172                         printk("%s: no CBR bandwidth free.\n", card->name);
2173                         return -ENOSR;
2174                 }
2175         }
2176
2177         if (tst_entries == 0) {
2178                 printk("%s: selected CBR bandwidth < granularity.\n",
2179                        card->name);
2180                 return -EINVAL;
2181         }
2182
2183         if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2184                 printk("%s: not enough CBR bandwidth free.\n", card->name);
2185                 return -ENOSR;
2186         }
2187
2188         vc->ntste = tst_entries;
2189
2190         card->tst_free = tst_free - tst_entries;
2191         if (test_bit(VCF_TX, &vc->flags)) {
2192                 if (tst_used == tst_entries)
2193                         return 0;
2194
2195                 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2196                         card->name, tst_used, tst_entries);
2197                 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2198                 return 0;
2199         }
2200
2201         OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2202         fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2203         return 0;
2204 }
2205
2206 static int
2207 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2208                   struct atm_vcc *vcc, struct atm_qos *qos)
2209 {
2210         struct rate_estimator *est = NULL;
2211         unsigned long flags;
2212         int tcr;
2213
2214         spin_lock_irqsave(&vc->lock, flags);
2215         if (vc->estimator) {
2216                 est = vc->estimator;
2217                 vc->estimator = NULL;
2218         }
2219         spin_unlock_irqrestore(&vc->lock, flags);
2220         if (est) {
2221                 del_timer_sync(&est->timer);
2222                 kfree(est);
2223         }
2224
2225         tcr = atm_pcr_goal(&qos->txtp);
2226         if (tcr == 0)
2227                 tcr = card->link_pcr;
2228
2229         vc->estimator = idt77252_init_est(vc, tcr);
2230
2231         vc->class = SCHED_UBR;
2232         vc->init_er = idt77252_rate_logindex(card, tcr);
2233         vc->lacr = vc->init_er;
2234         if (tcr < 0)
2235                 vc->max_er = vc->init_er;
2236         else
2237                 vc->max_er = 0xff;
2238
2239         return 0;
2240 }
2241
2242 static int
2243 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2244                  struct atm_vcc *vcc, struct atm_qos *qos)
2245 {
2246         int error;
2247
2248         if (test_bit(VCF_TX, &vc->flags))
2249                 return -EBUSY;
2250
2251         switch (qos->txtp.traffic_class) {
2252                 case ATM_CBR:
2253                         vc->class = SCHED_CBR;
2254                         break;
2255
2256                 case ATM_UBR:
2257                         vc->class = SCHED_UBR;
2258                         break;
2259
2260                 case ATM_VBR:
2261                 case ATM_ABR:
2262                 default:
2263                         return -EPROTONOSUPPORT;
2264         }
2265
2266         vc->scq = alloc_scq(card, vc->class);
2267         if (!vc->scq) {
2268                 printk("%s: can't get SCQ.\n", card->name);
2269                 return -ENOMEM;
2270         }
2271
2272         vc->scq->scd = get_free_scd(card, vc);
2273         if (vc->scq->scd == 0) {
2274                 printk("%s: no SCD available.\n", card->name);
2275                 free_scq(card, vc->scq);
2276                 return -ENOMEM;
2277         }
2278
2279         fill_scd(card, vc->scq, vc->class);
2280
2281         if (set_tct(card, vc)) {
2282                 printk("%s: class %d not supported.\n",
2283                        card->name, qos->txtp.traffic_class);
2284
2285                 card->scd2vc[vc->scd_index] = NULL;
2286                 free_scq(card, vc->scq);
2287                 return -EPROTONOSUPPORT;
2288         }
2289
2290         switch (vc->class) {
2291                 case SCHED_CBR:
2292                         error = idt77252_init_cbr(card, vc, vcc, qos);
2293                         if (error) {
2294                                 card->scd2vc[vc->scd_index] = NULL;
2295                                 free_scq(card, vc->scq);
2296                                 return error;
2297                         }
2298
2299                         clear_bit(VCF_IDLE, &vc->flags);
2300                         writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2301                         break;
2302
2303                 case SCHED_UBR:
2304                         error = idt77252_init_ubr(card, vc, vcc, qos);
2305                         if (error) {
2306                                 card->scd2vc[vc->scd_index] = NULL;
2307                                 free_scq(card, vc->scq);
2308                                 return error;
2309                         }
2310
2311                         set_bit(VCF_IDLE, &vc->flags);
2312                         break;
2313         }
2314
2315         vc->tx_vcc = vcc;
2316         set_bit(VCF_TX, &vc->flags);
2317         return 0;
2318 }
2319
2320 static int
2321 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2322                  struct atm_vcc *vcc, struct atm_qos *qos)
2323 {
2324         unsigned long flags;
2325         unsigned long addr;
2326         u32 rcte = 0;
2327
2328         if (test_bit(VCF_RX, &vc->flags))
2329                 return -EBUSY;
2330
2331         vc->rx_vcc = vcc;
2332         set_bit(VCF_RX, &vc->flags);
2333
2334         if ((vcc->vci == 3) || (vcc->vci == 4))
2335                 return 0;
2336
2337         flush_rx_pool(card, &vc->rcv.rx_pool);
2338
2339         rcte |= SAR_RCTE_CONNECTOPEN;
2340         rcte |= SAR_RCTE_RAWCELLINTEN;
2341
2342         switch (qos->aal) {
2343                 case ATM_AAL0:
2344                         rcte |= SAR_RCTE_RCQ;
2345                         break;
2346                 case ATM_AAL1:
2347                         rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2348                         break;
2349                 case ATM_AAL34:
2350                         rcte |= SAR_RCTE_AAL34;
2351                         break;
2352                 case ATM_AAL5:
2353                         rcte |= SAR_RCTE_AAL5;
2354                         break;
2355                 default:
2356                         rcte |= SAR_RCTE_RCQ;
2357                         break;
2358         }
2359
2360         if (qos->aal != ATM_AAL5)
2361                 rcte |= SAR_RCTE_FBP_1;
2362         else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2363                 rcte |= SAR_RCTE_FBP_3;
2364         else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2365                 rcte |= SAR_RCTE_FBP_2;
2366         else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2367                 rcte |= SAR_RCTE_FBP_1;
2368         else
2369                 rcte |= SAR_RCTE_FBP_01;
2370
2371         addr = card->rct_base + (vc->index << 2);
2372
2373         OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2374         write_sram(card, addr, rcte);
2375
2376         spin_lock_irqsave(&card->cmd_lock, flags);
2377         writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2378         waitfor_idle(card);
2379         spin_unlock_irqrestore(&card->cmd_lock, flags);
2380
2381         return 0;
2382 }
2383
2384 static int
2385 idt77252_open(struct atm_vcc *vcc)
2386 {
2387         struct atm_dev *dev = vcc->dev;
2388         struct idt77252_dev *card = dev->dev_data;
2389         struct vc_map *vc;
2390         unsigned int index;
2391         unsigned int inuse;
2392         int error;
2393         int vci = vcc->vci;
2394         short vpi = vcc->vpi;
2395
2396         if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2397                 return 0;
2398
2399         if (vpi >= (1 << card->vpibits)) {
2400                 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2401                 return -EINVAL;
2402         }
2403
2404         if (vci >= (1 << card->vcibits)) {
2405                 printk("%s: unsupported VCI: %d\n", card->name, vci);
2406                 return -EINVAL;
2407         }
2408
2409         set_bit(ATM_VF_ADDR, &vcc->flags);
2410
2411         mutex_lock(&card->mutex);
2412
2413         OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2414
2415         switch (vcc->qos.aal) {
2416         case ATM_AAL0:
2417         case ATM_AAL1:
2418         case ATM_AAL5:
2419                 break;
2420         default:
2421                 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2422                 mutex_unlock(&card->mutex);
2423                 return -EPROTONOSUPPORT;
2424         }
2425
2426         index = VPCI2VC(card, vpi, vci);
2427         if (!card->vcs[index]) {
2428                 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2429                 if (!card->vcs[index]) {
2430                         printk("%s: can't alloc vc in open()\n", card->name);
2431                         mutex_unlock(&card->mutex);
2432                         return -ENOMEM;
2433                 }
2434                 card->vcs[index]->card = card;
2435                 card->vcs[index]->index = index;
2436
2437                 spin_lock_init(&card->vcs[index]->lock);
2438         }
2439         vc = card->vcs[index];
2440
2441         vcc->dev_data = vc;
2442
2443         IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2444                 card->name, vc->index, vcc->vpi, vcc->vci,
2445                 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2446                 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2447                 vcc->qos.rxtp.max_sdu);
2448
2449         inuse = 0;
2450         if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2451             test_bit(VCF_TX, &vc->flags))
2452                 inuse = 1;
2453         if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2454             test_bit(VCF_RX, &vc->flags))
2455                 inuse += 2;
2456
2457         if (inuse) {
2458                 printk("%s: %s vci already in use.\n", card->name,
2459                        inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2460                 mutex_unlock(&card->mutex);
2461                 return -EADDRINUSE;
2462         }
2463
2464         if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2465                 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2466                 if (error) {
2467                         mutex_unlock(&card->mutex);
2468                         return error;
2469                 }
2470         }
2471
2472         if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2473                 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2474                 if (error) {
2475                         mutex_unlock(&card->mutex);
2476                         return error;
2477                 }
2478         }
2479
2480         set_bit(ATM_VF_READY, &vcc->flags);
2481
2482         mutex_unlock(&card->mutex);
2483         return 0;
2484 }
2485
2486 static void
2487 idt77252_close(struct atm_vcc *vcc)
2488 {
2489         struct atm_dev *dev = vcc->dev;
2490         struct idt77252_dev *card = dev->dev_data;
2491         struct vc_map *vc = vcc->dev_data;
2492         unsigned long flags;
2493         unsigned long addr;
2494         unsigned long timeout;
2495
2496         mutex_lock(&card->mutex);
2497
2498         IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2499                 card->name, vc->index, vcc->vpi, vcc->vci);
2500
2501         clear_bit(ATM_VF_READY, &vcc->flags);
2502
2503         if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2504
2505                 spin_lock_irqsave(&vc->lock, flags);
2506                 clear_bit(VCF_RX, &vc->flags);
2507                 vc->rx_vcc = NULL;
2508                 spin_unlock_irqrestore(&vc->lock, flags);
2509
2510                 if ((vcc->vci == 3) || (vcc->vci == 4))
2511                         goto done;
2512
2513                 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2514
2515                 spin_lock_irqsave(&card->cmd_lock, flags);
2516                 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2517                 waitfor_idle(card);
2518                 spin_unlock_irqrestore(&card->cmd_lock, flags);
2519
2520                 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2521                         DPRINTK("%s: closing a VC with pending rx buffers.\n",
2522                                 card->name);
2523
2524                         recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2525                 }
2526         }
2527
2528 done:
2529         if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2530
2531                 spin_lock_irqsave(&vc->lock, flags);
2532                 clear_bit(VCF_TX, &vc->flags);
2533                 clear_bit(VCF_IDLE, &vc->flags);
2534                 clear_bit(VCF_RSV, &vc->flags);
2535                 vc->tx_vcc = NULL;
2536
2537                 if (vc->estimator) {
2538                         del_timer(&vc->estimator->timer);
2539                         kfree(vc->estimator);
2540                         vc->estimator = NULL;
2541                 }
2542                 spin_unlock_irqrestore(&vc->lock, flags);
2543
2544                 timeout = 5 * 1000;
2545                 while (atomic_read(&vc->scq->used) > 0) {
2546                         timeout = msleep_interruptible(timeout);
2547                         if (!timeout) {
2548                                 pr_warn("%s: SCQ drain timeout: %u used\n",
2549                                         card->name, atomic_read(&vc->scq->used));
2550                                 break;
2551                         }
2552                 }
2553
2554                 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2555                 clear_scd(card, vc->scq, vc->class);
2556
2557                 if (vc->class == SCHED_CBR) {
2558                         clear_tst(card, vc);
2559                         card->tst_free += vc->ntste;
2560                         vc->ntste = 0;
2561                 }
2562
2563                 card->scd2vc[vc->scd_index] = NULL;
2564                 free_scq(card, vc->scq);
2565         }
2566
2567         mutex_unlock(&card->mutex);
2568 }
2569
2570 static int
2571 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2572 {
2573         struct atm_dev *dev = vcc->dev;
2574         struct idt77252_dev *card = dev->dev_data;
2575         struct vc_map *vc = vcc->dev_data;
2576         int error = 0;
2577
2578         mutex_lock(&card->mutex);
2579
2580         if (qos->txtp.traffic_class != ATM_NONE) {
2581                 if (!test_bit(VCF_TX, &vc->flags)) {
2582                         error = idt77252_init_tx(card, vc, vcc, qos);
2583                         if (error)
2584                                 goto out;
2585                 } else {
2586                         switch (qos->txtp.traffic_class) {
2587                         case ATM_CBR:
2588                                 error = idt77252_init_cbr(card, vc, vcc, qos);
2589                                 if (error)
2590                                         goto out;
2591                                 break;
2592
2593                         case ATM_UBR:
2594                                 error = idt77252_init_ubr(card, vc, vcc, qos);
2595                                 if (error)
2596                                         goto out;
2597
2598                                 if (!test_bit(VCF_IDLE, &vc->flags)) {
2599                                         writel(TCMDQ_LACR | (vc->lacr << 16) |
2600                                                vc->index, SAR_REG_TCMDQ);
2601                                 }
2602                                 break;
2603
2604                         case ATM_VBR:
2605                         case ATM_ABR:
2606                                 error = -EOPNOTSUPP;
2607                                 goto out;
2608                         }
2609                 }
2610         }
2611
2612         if ((qos->rxtp.traffic_class != ATM_NONE) &&
2613             !test_bit(VCF_RX, &vc->flags)) {
2614                 error = idt77252_init_rx(card, vc, vcc, qos);
2615                 if (error)
2616                         goto out;
2617         }
2618
2619         memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2620
2621         set_bit(ATM_VF_HASQOS, &vcc->flags);
2622
2623 out:
2624         mutex_unlock(&card->mutex);
2625         return error;
2626 }
2627
2628 static int
2629 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2630 {
2631         struct idt77252_dev *card = dev->dev_data;
2632         int i, left;
2633
2634         left = (int) *pos;
2635         if (!left--)
2636                 return sprintf(page, "IDT77252 Interrupts:\n");
2637         if (!left--)
2638                 return sprintf(page, "TSIF:  %lu\n", card->irqstat[15]);
2639         if (!left--)
2640                 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2641         if (!left--)
2642                 return sprintf(page, "TSQF:  %lu\n", card->irqstat[12]);
2643         if (!left--)
2644                 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2645         if (!left--)
2646                 return sprintf(page, "PHYI:  %lu\n", card->irqstat[10]);
2647         if (!left--)
2648                 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2649         if (!left--)
2650                 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2651         if (!left--)
2652                 return sprintf(page, "RSQF:  %lu\n", card->irqstat[6]);
2653         if (!left--)
2654                 return sprintf(page, "EPDU:  %lu\n", card->irqstat[5]);
2655         if (!left--)
2656                 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2657         if (!left--)
2658                 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2659         if (!left--)
2660                 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2661         if (!left--)
2662                 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2663         if (!left--)
2664                 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2665
2666         for (i = 0; i < card->tct_size; i++) {
2667                 unsigned long tct;
2668                 struct atm_vcc *vcc;
2669                 struct vc_map *vc;
2670                 char *p;
2671
2672                 vc = card->vcs[i];
2673                 if (!vc)
2674                         continue;
2675
2676                 vcc = NULL;
2677                 if (vc->tx_vcc)
2678                         vcc = vc->tx_vcc;
2679                 if (!vcc)
2680                         continue;
2681                 if (left--)
2682                         continue;
2683
2684                 p = page;
2685                 p += sprintf(p, "  %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2686                 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2687
2688                 for (i = 0; i < 8; i++)
2689                         p += sprintf(p, " %08x", read_sram(card, tct + i));
2690                 p += sprintf(p, "\n");
2691                 return p - page;
2692         }
2693         return 0;
2694 }
2695
2696 /*****************************************************************************/
2697 /*                                                                           */
2698 /* Interrupt handler                                                         */
2699 /*                                                                           */
2700 /*****************************************************************************/
2701
2702 static void
2703 idt77252_collect_stat(struct idt77252_dev *card)
2704 {
2705         (void) readl(SAR_REG_CDC);
2706         (void) readl(SAR_REG_VPEC);
2707         (void) readl(SAR_REG_ICC);
2708
2709 }
2710
2711 static irqreturn_t
2712 idt77252_interrupt(int irq, void *dev_id)
2713 {
2714         struct idt77252_dev *card = dev_id;
2715         u32 stat;
2716
2717         stat = readl(SAR_REG_STAT) & 0xffff;
2718         if (!stat)      /* no interrupt for us */
2719                 return IRQ_NONE;
2720
2721         if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2722                 printk("%s: Re-entering irq_handler()\n", card->name);
2723                 goto out;
2724         }
2725
2726         writel(stat, SAR_REG_STAT);     /* reset interrupt */
2727
2728         if (stat & SAR_STAT_TSIF) {     /* entry written to TSQ  */
2729                 INTPRINTK("%s: TSIF\n", card->name);
2730                 card->irqstat[15]++;
2731                 idt77252_tx(card);
2732         }
2733         if (stat & SAR_STAT_TXICP) {    /* Incomplete CS-PDU has  */
2734                 INTPRINTK("%s: TXICP\n", card->name);
2735                 card->irqstat[14]++;
2736 #ifdef CONFIG_ATM_IDT77252_DEBUG
2737                 idt77252_tx_dump(card);
2738 #endif
2739         }
2740         if (stat & SAR_STAT_TSQF) {     /* TSQ 7/8 full           */
2741                 INTPRINTK("%s: TSQF\n", card->name);
2742                 card->irqstat[12]++;
2743                 idt77252_tx(card);
2744         }
2745         if (stat & SAR_STAT_TMROF) {    /* Timer overflow         */
2746                 INTPRINTK("%s: TMROF\n", card->name);
2747                 card->irqstat[11]++;
2748                 idt77252_collect_stat(card);
2749         }
2750
2751         if (stat & SAR_STAT_EPDU) {     /* Got complete CS-PDU    */
2752                 INTPRINTK("%s: EPDU\n", card->name);
2753                 card->irqstat[5]++;
2754                 idt77252_rx(card);
2755         }
2756         if (stat & SAR_STAT_RSQAF) {    /* RSQ is 7/8 full        */
2757                 INTPRINTK("%s: RSQAF\n", card->name);
2758                 card->irqstat[1]++;
2759                 idt77252_rx(card);
2760         }
2761         if (stat & SAR_STAT_RSQF) {     /* RSQ is full            */
2762                 INTPRINTK("%s: RSQF\n", card->name);
2763                 card->irqstat[6]++;
2764                 idt77252_rx(card);
2765         }
2766         if (stat & SAR_STAT_RAWCF) {    /* Raw cell received      */
2767                 INTPRINTK("%s: RAWCF\n", card->name);
2768                 card->irqstat[4]++;
2769                 idt77252_rx_raw(card);
2770         }
2771
2772         if (stat & SAR_STAT_PHYI) {     /* PHY device interrupt   */
2773                 INTPRINTK("%s: PHYI", card->name);
2774                 card->irqstat[10]++;
2775                 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2776                         card->atmdev->phy->interrupt(card->atmdev);
2777         }
2778
2779         if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2780                     SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2781
2782                 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2783
2784                 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2785
2786                 if (stat & SAR_STAT_FBQ0A)
2787                         card->irqstat[2]++;
2788                 if (stat & SAR_STAT_FBQ1A)
2789                         card->irqstat[3]++;
2790                 if (stat & SAR_STAT_FBQ2A)
2791                         card->irqstat[7]++;
2792                 if (stat & SAR_STAT_FBQ3A)
2793                         card->irqstat[8]++;
2794
2795                 schedule_work(&card->tqueue);
2796         }
2797
2798 out:
2799         clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2800         return IRQ_HANDLED;
2801 }
2802
2803 static void
2804 idt77252_softint(struct work_struct *work)
2805 {
2806         struct idt77252_dev *card =
2807                 container_of(work, struct idt77252_dev, tqueue);
2808         u32 stat;
2809         int done;
2810
2811         for (done = 1; ; done = 1) {
2812                 stat = readl(SAR_REG_STAT) >> 16;
2813
2814                 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2815                         add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2816                         done = 0;
2817                 }
2818
2819                 stat >>= 4;
2820                 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2821                         add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2822                         done = 0;
2823                 }
2824
2825                 stat >>= 4;
2826                 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2827                         add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2828                         done = 0;
2829                 }
2830
2831                 stat >>= 4;
2832                 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2833                         add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2834                         done = 0;
2835                 }
2836
2837                 if (done)
2838                         break;
2839         }
2840
2841         writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2842 }
2843
2844
2845 static int
2846 open_card_oam(struct idt77252_dev *card)
2847 {
2848         unsigned long flags;
2849         unsigned long addr;
2850         struct vc_map *vc;
2851         int vpi, vci;
2852         int index;
2853         u32 rcte;
2854
2855         for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2856                 for (vci = 3; vci < 5; vci++) {
2857                         index = VPCI2VC(card, vpi, vci);
2858
2859                         vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2860                         if (!vc) {
2861                                 printk("%s: can't alloc vc\n", card->name);
2862                                 return -ENOMEM;
2863                         }
2864                         vc->index = index;
2865                         card->vcs[index] = vc;
2866
2867                         flush_rx_pool(card, &vc->rcv.rx_pool);
2868
2869                         rcte = SAR_RCTE_CONNECTOPEN |
2870                                SAR_RCTE_RAWCELLINTEN |
2871                                SAR_RCTE_RCQ |
2872                                SAR_RCTE_FBP_1;
2873
2874                         addr = card->rct_base + (vc->index << 2);
2875                         write_sram(card, addr, rcte);
2876
2877                         spin_lock_irqsave(&card->cmd_lock, flags);
2878                         writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2879                                SAR_REG_CMD);
2880                         waitfor_idle(card);
2881                         spin_unlock_irqrestore(&card->cmd_lock, flags);
2882                 }
2883         }
2884
2885         return 0;
2886 }
2887
2888 static void
2889 close_card_oam(struct idt77252_dev *card)
2890 {
2891         unsigned long flags;
2892         unsigned long addr;
2893         struct vc_map *vc;
2894         int vpi, vci;
2895         int index;
2896
2897         for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2898                 for (vci = 3; vci < 5; vci++) {
2899                         index = VPCI2VC(card, vpi, vci);
2900                         vc = card->vcs[index];
2901
2902                         addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2903
2904                         spin_lock_irqsave(&card->cmd_lock, flags);
2905                         writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2906                                SAR_REG_CMD);
2907                         waitfor_idle(card);
2908                         spin_unlock_irqrestore(&card->cmd_lock, flags);
2909
2910                         if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2911                                 DPRINTK("%s: closing a VC "
2912                                         "with pending rx buffers.\n",
2913                                         card->name);
2914
2915                                 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2916                         }
2917                 }
2918         }
2919 }
2920
2921 static int
2922 open_card_ubr0(struct idt77252_dev *card)
2923 {
2924         struct vc_map *vc;
2925
2926         vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2927         if (!vc) {
2928                 printk("%s: can't alloc vc\n", card->name);
2929                 return -ENOMEM;
2930         }
2931         card->vcs[0] = vc;
2932         vc->class = SCHED_UBR0;
2933
2934         vc->scq = alloc_scq(card, vc->class);
2935         if (!vc->scq) {
2936                 printk("%s: can't get SCQ.\n", card->name);
2937                 return -ENOMEM;
2938         }
2939
2940         card->scd2vc[0] = vc;
2941         vc->scd_index = 0;
2942         vc->scq->scd = card->scd_base;
2943
2944         fill_scd(card, vc->scq, vc->class);
2945
2946         write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
2947         write_sram(card, card->tct_base + 1, 0);
2948         write_sram(card, card->tct_base + 2, 0);
2949         write_sram(card, card->tct_base + 3, 0);
2950         write_sram(card, card->tct_base + 4, 0);
2951         write_sram(card, card->tct_base + 5, 0);
2952         write_sram(card, card->tct_base + 6, 0);
2953         write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
2954
2955         clear_bit(VCF_IDLE, &vc->flags);
2956         writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
2957         return 0;
2958 }
2959
2960 static int
2961 idt77252_dev_open(struct idt77252_dev *card)
2962 {
2963         u32 conf;
2964
2965         if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
2966                 printk("%s: SAR not yet initialized.\n", card->name);
2967                 return -1;
2968         }
2969
2970         conf = SAR_CFG_RXPTH|   /* enable receive path                  */
2971             SAR_RX_DELAY |      /* interrupt on complete PDU            */
2972             SAR_CFG_RAWIE |     /* interrupt enable on raw cells        */
2973             SAR_CFG_RQFIE |     /* interrupt on RSQ almost full         */
2974             SAR_CFG_TMOIE |     /* interrupt on timer overflow          */
2975             SAR_CFG_FBIE |      /* interrupt on low free buffers        */
2976             SAR_CFG_TXEN |      /* transmit operation enable            */
2977             SAR_CFG_TXINT |     /* interrupt on transmit status         */
2978             SAR_CFG_TXUIE |     /* interrupt on transmit underrun       */
2979             SAR_CFG_TXSFI |     /* interrupt on TSQ almost full         */
2980             SAR_CFG_PHYIE       /* enable PHY interrupts                */
2981             ;
2982
2983 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
2984         /* Test RAW cell receive. */
2985         conf |= SAR_CFG_VPECA;
2986 #endif
2987
2988         writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
2989
2990         if (open_card_oam(card)) {
2991                 printk("%s: Error initializing OAM.\n", card->name);
2992                 return -1;
2993         }
2994
2995         if (open_card_ubr0(card)) {
2996                 printk("%s: Error initializing UBR0.\n", card->name);
2997                 return -1;
2998         }
2999
3000         IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3001         return 0;
3002 }
3003
3004 static void idt77252_dev_close(struct atm_dev *dev)
3005 {
3006         struct idt77252_dev *card = dev->dev_data;
3007         u32 conf;
3008
3009         close_card_oam(card);
3010
3011         conf = SAR_CFG_RXPTH |  /* enable receive path           */
3012             SAR_RX_DELAY |      /* interrupt on complete PDU     */
3013             SAR_CFG_RAWIE |     /* interrupt enable on raw cells */
3014             SAR_CFG_RQFIE |     /* interrupt on RSQ almost full  */
3015             SAR_CFG_TMOIE |     /* interrupt on timer overflow   */
3016             SAR_CFG_FBIE |      /* interrupt on low free buffers */
3017             SAR_CFG_TXEN |      /* transmit operation enable     */
3018             SAR_CFG_TXINT |     /* interrupt on transmit status  */
3019             SAR_CFG_TXUIE |     /* interrupt on xmit underrun    */
3020             SAR_CFG_TXSFI       /* interrupt on TSQ almost full  */
3021             ;
3022
3023         writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3024
3025         DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3026 }
3027
3028
3029 /*****************************************************************************/
3030 /*                                                                           */
3031 /* Initialisation and Deinitialization of IDT77252                           */
3032 /*                                                                           */
3033 /*****************************************************************************/
3034
3035
3036 static void
3037 deinit_card(struct idt77252_dev *card)
3038 {
3039         struct sk_buff *skb;
3040         int i, j;
3041
3042         if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3043                 printk("%s: SAR not yet initialized.\n", card->name);
3044                 return;
3045         }
3046         DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3047
3048         writel(0, SAR_REG_CFG);
3049
3050         if (card->atmdev)
3051                 atm_dev_deregister(card->atmdev);
3052
3053         for (i = 0; i < 4; i++) {
3054                 for (j = 0; j < FBQ_SIZE; j++) {
3055                         skb = card->sbpool[i].skb[j];
3056                         if (skb) {
3057                                 dma_unmap_single(&card->pcidev->dev,
3058                                                  IDT77252_PRV_PADDR(skb),
3059                                                  (skb_end_pointer(skb) -
3060                                                   skb->data),
3061                                                  DMA_FROM_DEVICE);
3062                                 card->sbpool[i].skb[j] = NULL;
3063                                 dev_kfree_skb(skb);
3064                         }
3065                 }
3066         }
3067
3068         vfree(card->soft_tst);
3069
3070         vfree(card->scd2vc);
3071
3072         vfree(card->vcs);
3073
3074         if (card->raw_cell_hnd) {
3075                 dma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32),
3076                                   card->raw_cell_hnd, card->raw_cell_paddr);
3077         }
3078
3079         if (card->rsq.base) {
3080                 DIPRINTK("%s: Release RSQ ...\n", card->name);
3081                 deinit_rsq(card);
3082         }
3083
3084         if (card->tsq.base) {
3085                 DIPRINTK("%s: Release TSQ ...\n", card->name);
3086                 deinit_tsq(card);
3087         }
3088
3089         DIPRINTK("idt77252: Release IRQ.\n");
3090         free_irq(card->pcidev->irq, card);
3091
3092         for (i = 0; i < 4; i++) {
3093                 if (card->fbq[i])
3094                         iounmap(card->fbq[i]);
3095         }
3096
3097         if (card->membase)
3098                 iounmap(card->membase);
3099
3100         clear_bit(IDT77252_BIT_INIT, &card->flags);
3101         DIPRINTK("%s: Card deinitialized.\n", card->name);
3102 }
3103
3104
3105 static void init_sram(struct idt77252_dev *card)
3106 {
3107         int i;
3108
3109         for (i = 0; i < card->sramsize; i += 4)
3110                 write_sram(card, (i >> 2), 0);
3111
3112         /* set SRAM layout for THIS card */
3113         if (card->sramsize == (512 * 1024)) {
3114                 card->tct_base = SAR_SRAM_TCT_128_BASE;
3115                 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3116                     / SAR_SRAM_TCT_SIZE;
3117                 card->rct_base = SAR_SRAM_RCT_128_BASE;
3118                 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3119                     / SAR_SRAM_RCT_SIZE;
3120                 card->rt_base = SAR_SRAM_RT_128_BASE;
3121                 card->scd_base = SAR_SRAM_SCD_128_BASE;
3122                 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3123                     / SAR_SRAM_SCD_SIZE;
3124                 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3125                 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3126                 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3127                 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3128                 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3129                 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3130                 card->fifo_size = SAR_RXFD_SIZE_32K;
3131         } else {
3132                 card->tct_base = SAR_SRAM_TCT_32_BASE;
3133                 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3134                     / SAR_SRAM_TCT_SIZE;
3135                 card->rct_base = SAR_SRAM_RCT_32_BASE;
3136                 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3137                     / SAR_SRAM_RCT_SIZE;
3138                 card->rt_base = SAR_SRAM_RT_32_BASE;
3139                 card->scd_base = SAR_SRAM_SCD_32_BASE;
3140                 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3141                     / SAR_SRAM_SCD_SIZE;
3142                 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3143                 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3144                 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3145                 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3146                 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3147                 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3148                 card->fifo_size = SAR_RXFD_SIZE_4K;
3149         }
3150
3151         /* Initialize TCT */
3152         for (i = 0; i < card->tct_size; i++) {
3153                 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3154                 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3155                 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3156                 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3157                 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3158                 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3159                 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3160                 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3161         }
3162
3163         /* Initialize RCT */
3164         for (i = 0; i < card->rct_size; i++) {
3165                 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3166                                     (u32) SAR_RCTE_RAWCELLINTEN);
3167                 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3168                                     (u32) 0);
3169                 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3170                                     (u32) 0);
3171                 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3172                                     (u32) 0xffffffff);
3173         }
3174
3175         writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3176         writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3177         writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3178         writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3179
3180         /* Initialize rate table  */
3181         for (i = 0; i < 256; i++) {
3182                 write_sram(card, card->rt_base + i, log_to_rate[i]);
3183         }
3184
3185         for (i = 0; i < 128; i++) {
3186                 unsigned int tmp;
3187
3188                 tmp  = rate_to_log[(i << 2) + 0] << 0;
3189                 tmp |= rate_to_log[(i << 2) + 1] << 8;
3190                 tmp |= rate_to_log[(i << 2) + 2] << 16;
3191                 tmp |= rate_to_log[(i << 2) + 3] << 24;
3192                 write_sram(card, card->rt_base + 256 + i, tmp);
3193         }
3194
3195 #if 0 /* Fill RDF and AIR tables. */
3196         for (i = 0; i < 128; i++) {
3197                 unsigned int tmp;
3198
3199                 tmp = RDF[0][(i << 1) + 0] << 16;
3200                 tmp |= RDF[0][(i << 1) + 1] << 0;
3201                 write_sram(card, card->rt_base + 512 + i, tmp);
3202         }
3203
3204         for (i = 0; i < 128; i++) {
3205                 unsigned int tmp;
3206
3207                 tmp = AIR[0][(i << 1) + 0] << 16;
3208                 tmp |= AIR[0][(i << 1) + 1] << 0;
3209                 write_sram(card, card->rt_base + 640 + i, tmp);
3210         }
3211 #endif
3212
3213         IPRINTK("%s: initialize rate table ...\n", card->name);
3214         writel(card->rt_base << 2, SAR_REG_RTBL);
3215
3216         /* Initialize TSTs */
3217         IPRINTK("%s: initialize TST ...\n", card->name);
3218         card->tst_free = card->tst_size - 2;    /* last two are jumps */
3219
3220         for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3221                 write_sram(card, i, TSTE_OPC_VAR);
3222         write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3223         idt77252_sram_write_errors = 1;
3224         write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3225         idt77252_sram_write_errors = 0;
3226         for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3227                 write_sram(card, i, TSTE_OPC_VAR);
3228         write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3229         idt77252_sram_write_errors = 1;
3230         write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3231         idt77252_sram_write_errors = 0;
3232
3233         card->tst_index = 0;
3234         writel(card->tst[0] << 2, SAR_REG_TSTB);
3235
3236         /* Initialize ABRSTD and Receive FIFO */
3237         IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3238         writel(card->abrst_size | (card->abrst_base << 2),
3239                SAR_REG_ABRSTD);
3240
3241         IPRINTK("%s: initialize receive fifo ...\n", card->name);
3242         writel(card->fifo_size | (card->fifo_base << 2),
3243                SAR_REG_RXFD);
3244
3245         IPRINTK("%s: SRAM initialization complete.\n", card->name);
3246 }
3247
3248 static int init_card(struct atm_dev *dev)
3249 {
3250         struct idt77252_dev *card = dev->dev_data;
3251         struct pci_dev *pcidev = card->pcidev;
3252         unsigned long tmpl, modl;
3253         unsigned int linkrate, rsvdcr;
3254         unsigned int tst_entries;
3255         struct net_device *tmp;
3256         char tname[10];
3257
3258         u32 size;
3259         u_char pci_byte;
3260         u32 conf;
3261         int i, k;
3262
3263         if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3264                 printk("Error: SAR already initialized.\n");
3265                 return -1;
3266         }
3267
3268 /*****************************************************************/
3269 /*   P C I   C O N F I G U R A T I O N                           */
3270 /*****************************************************************/
3271
3272         /* Set PCI Retry-Timeout and TRDY timeout */
3273         IPRINTK("%s: Checking PCI retries.\n", card->name);
3274         if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3275                 printk("%s: can't read PCI retry timeout.\n", card->name);
3276                 deinit_card(card);
3277                 return -1;
3278         }
3279         if (pci_byte != 0) {
3280                 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3281                         card->name, pci_byte);
3282                 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3283                         printk("%s: can't set PCI retry timeout.\n",
3284                                card->name);
3285                         deinit_card(card);
3286                         return -1;
3287                 }
3288         }
3289         IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3290         if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3291                 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3292                 deinit_card(card);
3293                 return -1;
3294         }
3295         if (pci_byte != 0) {
3296                 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3297                         card->name, pci_byte);
3298                 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3299                         printk("%s: can't set PCI TRDY timeout.\n", card->name);
3300                         deinit_card(card);
3301                         return -1;
3302                 }
3303         }
3304         /* Reset Timer register */
3305         if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3306                 printk("%s: resetting timer overflow.\n", card->name);
3307                 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3308         }
3309         IPRINTK("%s: Request IRQ ... ", card->name);
3310         if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED,
3311                         card->name, card) != 0) {
3312                 printk("%s: can't allocate IRQ.\n", card->name);
3313                 deinit_card(card);
3314                 return -1;
3315         }
3316         IPRINTK("got %d.\n", pcidev->irq);
3317
3318 /*****************************************************************/
3319 /*   C H E C K   A N D   I N I T   S R A M                       */
3320 /*****************************************************************/
3321
3322         IPRINTK("%s: Initializing SRAM\n", card->name);
3323
3324         /* preset size of connecton table, so that init_sram() knows about it */
3325         conf =  SAR_CFG_TX_FIFO_SIZE_9 |        /* Use maximum fifo size */
3326                 SAR_CFG_RXSTQ_SIZE_8k |         /* Receive Status Queue is 8k */
3327                 SAR_CFG_IDLE_CLP |              /* Set CLP on idle cells */
3328 #ifndef ATM_IDT77252_SEND_IDLE
3329                 SAR_CFG_NO_IDLE |               /* Do not send idle cells */
3330 #endif
3331                 0;
3332
3333         if (card->sramsize == (512 * 1024))
3334                 conf |= SAR_CFG_CNTBL_1k;
3335         else
3336                 conf |= SAR_CFG_CNTBL_512;
3337
3338         switch (vpibits) {
3339         case 0:
3340                 conf |= SAR_CFG_VPVCS_0;
3341                 break;
3342         default:
3343         case 1:
3344                 conf |= SAR_CFG_VPVCS_1;
3345                 break;
3346         case 2:
3347                 conf |= SAR_CFG_VPVCS_2;
3348                 break;
3349         case 8:
3350                 conf |= SAR_CFG_VPVCS_8;
3351                 break;
3352         }
3353
3354         writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3355
3356         init_sram(card);
3357
3358 /********************************************************************/
3359 /*  A L L O C   R A M   A N D   S E T   V A R I O U S   T H I N G S */
3360 /********************************************************************/
3361         /* Initialize TSQ */
3362         if (0 != init_tsq(card)) {
3363                 deinit_card(card);
3364                 return -1;
3365         }
3366         /* Initialize RSQ */
3367         if (0 != init_rsq(card)) {
3368                 deinit_card(card);
3369                 return -1;
3370         }
3371
3372         card->vpibits = vpibits;
3373         if (card->sramsize == (512 * 1024)) {
3374                 card->vcibits = 10 - card->vpibits;
3375         } else {
3376                 card->vcibits = 9 - card->vpibits;
3377         }
3378
3379         card->vcimask = 0;
3380         for (k = 0, i = 1; k < card->vcibits; k++) {
3381                 card->vcimask |= i;
3382                 i <<= 1;
3383         }
3384
3385         IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3386         writel(0, SAR_REG_VPM);
3387
3388         /* Little Endian Order   */
3389         writel(0, SAR_REG_GP);
3390
3391         /* Initialize RAW Cell Handle Register  */
3392         card->raw_cell_hnd = dma_alloc_coherent(&card->pcidev->dev,
3393                                                 2 * sizeof(u32),
3394                                                 &card->raw_cell_paddr,
3395                                                 GFP_KERNEL);
3396         if (!card->raw_cell_hnd) {
3397                 printk("%s: memory allocation failure.\n", card->name);
3398                 deinit_card(card);
3399                 return -1;
3400         }
3401         writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3402         IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3403                 card->raw_cell_hnd);
3404
3405         size = sizeof(struct vc_map *) * card->tct_size;
3406         IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3407         card->vcs = vzalloc(size);
3408         if (!card->vcs) {
3409                 printk("%s: memory allocation failure.\n", card->name);
3410                 deinit_card(card);
3411                 return -1;
3412         }
3413
3414         size = sizeof(struct vc_map *) * card->scd_size;
3415         IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3416                 card->name, size);
3417         card->scd2vc = vzalloc(size);
3418         if (!card->scd2vc) {
3419                 printk("%s: memory allocation failure.\n", card->name);
3420                 deinit_card(card);
3421                 return -1;
3422         }
3423
3424         size = sizeof(struct tst_info) * (card->tst_size - 2);
3425         IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3426                 card->name, size);
3427         card->soft_tst = vmalloc(size);
3428         if (!card->soft_tst) {
3429                 printk("%s: memory allocation failure.\n", card->name);
3430                 deinit_card(card);
3431                 return -1;
3432         }
3433         for (i = 0; i < card->tst_size - 2; i++) {
3434                 card->soft_tst[i].tste = TSTE_OPC_VAR;
3435                 card->soft_tst[i].vc = NULL;
3436         }
3437
3438         if (dev->phy == NULL) {
3439                 printk("%s: No LT device defined.\n", card->name);
3440                 deinit_card(card);
3441                 return -1;
3442         }
3443         if (dev->phy->ioctl == NULL) {
3444                 printk("%s: LT had no IOCTL function defined.\n", card->name);
3445                 deinit_card(card);
3446                 return -1;
3447         }
3448
3449 #ifdef  CONFIG_ATM_IDT77252_USE_SUNI
3450         /*
3451          * this is a jhs hack to get around special functionality in the
3452          * phy driver for the atecom hardware; the functionality doesn't
3453          * exist in the linux atm suni driver
3454          *
3455          * it isn't the right way to do things, but as the guy from NIST
3456          * said, talking about their measurement of the fine structure
3457          * constant, "it's good enough for government work."
3458          */
3459         linkrate = 149760000;
3460 #endif
3461
3462         card->link_pcr = (linkrate / 8 / 53);
3463         printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3464                card->name, linkrate, card->link_pcr);
3465
3466 #ifdef ATM_IDT77252_SEND_IDLE
3467         card->utopia_pcr = card->link_pcr;
3468 #else
3469         card->utopia_pcr = (160000000 / 8 / 54);
3470 #endif
3471
3472         rsvdcr = 0;
3473         if (card->utopia_pcr > card->link_pcr)
3474                 rsvdcr = card->utopia_pcr - card->link_pcr;
3475
3476         tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3477         modl = tmpl % (unsigned long)card->utopia_pcr;
3478         tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3479         if (modl)
3480                 tst_entries++;
3481         card->tst_free -= tst_entries;
3482         fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3483
3484 #ifdef HAVE_EEPROM
3485         idt77252_eeprom_init(card);
3486         printk("%s: EEPROM: %02x:", card->name,
3487                 idt77252_eeprom_read_status(card));
3488
3489         for (i = 0; i < 0x80; i++) {
3490                 printk(" %02x",
3491                 idt77252_eeprom_read_byte(card, i)
3492                 );
3493         }
3494         printk("\n");
3495 #endif /* HAVE_EEPROM */
3496
3497         /*
3498          * XXX: <hack>
3499          */
3500         sprintf(tname, "eth%d", card->index);
3501         tmp = dev_get_by_name(&init_net, tname);        /* jhs: was "tmp = dev_get(tname);" */
3502         if (tmp) {
3503                 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3504                 dev_put(tmp);
3505                 printk("%s: ESI %pM\n", card->name, card->atmdev->esi);
3506         }
3507         /*
3508          * XXX: </hack>
3509          */
3510
3511         /* Set Maximum Deficit Count for now. */
3512         writel(0xffff, SAR_REG_MDFCT);
3513
3514         set_bit(IDT77252_BIT_INIT, &card->flags);
3515
3516         XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3517         return 0;
3518 }
3519
3520
3521 /*****************************************************************************/
3522 /*                                                                           */
3523 /* Probing of IDT77252 ABR SAR                                               */
3524 /*                                                                           */
3525 /*****************************************************************************/
3526
3527
3528 static int idt77252_preset(struct idt77252_dev *card)
3529 {
3530         u16 pci_command;
3531
3532 /*****************************************************************/
3533 /*   P C I   C O N F I G U R A T I O N                           */
3534 /*****************************************************************/
3535
3536         XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3537                 card->name);
3538         if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3539                 printk("%s: can't read PCI_COMMAND.\n", card->name);
3540                 deinit_card(card);
3541                 return -1;
3542         }
3543         if (!(pci_command & PCI_COMMAND_IO)) {
3544                 printk("%s: PCI_COMMAND: %04x (???)\n",
3545                        card->name, pci_command);
3546                 deinit_card(card);
3547                 return (-1);
3548         }
3549         pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3550         if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3551                 printk("%s: can't write PCI_COMMAND.\n", card->name);
3552                 deinit_card(card);
3553                 return -1;
3554         }
3555 /*****************************************************************/
3556 /*   G E N E R I C   R E S E T                                   */
3557 /*****************************************************************/
3558
3559         /* Software reset */
3560         writel(SAR_CFG_SWRST, SAR_REG_CFG);
3561         mdelay(1);
3562         writel(0, SAR_REG_CFG);
3563
3564         IPRINTK("%s: Software resetted.\n", card->name);
3565         return 0;
3566 }
3567
3568
3569 static unsigned long probe_sram(struct idt77252_dev *card)
3570 {
3571         u32 data, addr;
3572
3573         writel(0, SAR_REG_DR0);
3574         writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3575
3576         for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3577                 writel(ATM_POISON, SAR_REG_DR0);
3578                 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3579
3580                 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3581                 data = readl(SAR_REG_DR0);
3582
3583                 if (data != 0)
3584                         break;
3585         }
3586
3587         return addr * sizeof(u32);
3588 }
3589
3590 static int idt77252_init_one(struct pci_dev *pcidev,
3591                              const struct pci_device_id *id)
3592 {
3593         static struct idt77252_dev **last = &idt77252_chain;
3594         static int index = 0;
3595
3596         unsigned long membase, srambase;
3597         struct idt77252_dev *card;
3598         struct atm_dev *dev;
3599         int i, err;
3600
3601
3602         if ((err = pci_enable_device(pcidev))) {
3603                 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3604                 return err;
3605         }
3606
3607         if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {
3608                 printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));
3609                 return err;
3610         }
3611
3612         card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3613         if (!card) {
3614                 printk("idt77252-%d: can't allocate private data\n", index);
3615                 err = -ENOMEM;
3616                 goto err_out_disable_pdev;
3617         }
3618         card->revision = pcidev->revision;
3619         card->index = index;
3620         card->pcidev = pcidev;
3621         sprintf(card->name, "idt77252-%d", card->index);
3622
3623         INIT_WORK(&card->tqueue, idt77252_softint);
3624
3625         membase = pci_resource_start(pcidev, 1);
3626         srambase = pci_resource_start(pcidev, 2);
3627
3628         mutex_init(&card->mutex);
3629         spin_lock_init(&card->cmd_lock);
3630         spin_lock_init(&card->tst_lock);
3631
3632         timer_setup(&card->tst_timer, tst_timer, 0);
3633
3634         /* Do the I/O remapping... */
3635         card->membase = ioremap(membase, 1024);
3636         if (!card->membase) {
3637                 printk("%s: can't ioremap() membase\n", card->name);
3638                 err = -EIO;
3639                 goto err_out_free_card;
3640         }
3641
3642         if (idt77252_preset(card)) {
3643                 printk("%s: preset failed\n", card->name);
3644                 err = -EIO;
3645                 goto err_out_iounmap;
3646         }
3647
3648         dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1,
3649                                NULL);
3650         if (!dev) {
3651                 printk("%s: can't register atm device\n", card->name);
3652                 err = -EIO;
3653                 goto err_out_iounmap;
3654         }
3655         dev->dev_data = card;
3656         card->atmdev = dev;
3657
3658 #ifdef  CONFIG_ATM_IDT77252_USE_SUNI
3659         suni_init(dev);
3660         if (!dev->phy) {
3661                 printk("%s: can't init SUNI\n", card->name);
3662                 err = -EIO;
3663                 goto err_out_deinit_card;
3664         }
3665 #endif  /* CONFIG_ATM_IDT77252_USE_SUNI */
3666
3667         card->sramsize = probe_sram(card);
3668
3669         for (i = 0; i < 4; i++) {
3670                 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3671                 if (!card->fbq[i]) {
3672                         printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3673                         err = -EIO;
3674                         goto err_out_deinit_card;
3675                 }
3676         }
3677
3678         printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3679                card->name, ((card->revision > 1) && (card->revision < 25)) ?
3680                'A' + card->revision - 1 : '?', membase, srambase,
3681                card->sramsize / 1024);
3682
3683         if (init_card(dev)) {
3684                 printk("%s: init_card failed\n", card->name);
3685                 err = -EIO;
3686                 goto err_out_deinit_card;
3687         }
3688
3689         dev->ci_range.vpi_bits = card->vpibits;
3690         dev->ci_range.vci_bits = card->vcibits;
3691         dev->link_rate = card->link_pcr;
3692
3693         if (dev->phy->start)
3694                 dev->phy->start(dev);
3695
3696         if (idt77252_dev_open(card)) {
3697                 printk("%s: dev_open failed\n", card->name);
3698                 err = -EIO;
3699                 goto err_out_stop;
3700         }
3701
3702         *last = card;
3703         last = &card->next;
3704         index++;
3705
3706         return 0;
3707
3708 err_out_stop:
3709         if (dev->phy->stop)
3710                 dev->phy->stop(dev);
3711
3712 err_out_deinit_card:
3713         deinit_card(card);
3714
3715 err_out_iounmap:
3716         iounmap(card->membase);
3717
3718 err_out_free_card:
3719         kfree(card);
3720
3721 err_out_disable_pdev:
3722         pci_disable_device(pcidev);
3723         return err;
3724 }
3725
3726 static const struct pci_device_id idt77252_pci_tbl[] =
3727 {
3728         { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 },
3729         { 0, }
3730 };
3731
3732 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3733
3734 static struct pci_driver idt77252_driver = {
3735         .name           = "idt77252",
3736         .id_table       = idt77252_pci_tbl,
3737         .probe          = idt77252_init_one,
3738 };
3739
3740 static int __init idt77252_init(void)
3741 {
3742         struct sk_buff *skb;
3743
3744         printk("%s: at %p\n", __func__, idt77252_init);
3745
3746         if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3747                               sizeof(struct idt77252_skb_prv)) {
3748                 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3749                        __func__, (unsigned long) sizeof(skb->cb),
3750                        (unsigned long) sizeof(struct atm_skb_data) +
3751                                        sizeof(struct idt77252_skb_prv));
3752                 return -EIO;
3753         }
3754
3755         return pci_register_driver(&idt77252_driver);
3756 }
3757
3758 static void __exit idt77252_exit(void)
3759 {
3760         struct idt77252_dev *card;
3761         struct atm_dev *dev;
3762
3763         pci_unregister_driver(&idt77252_driver);
3764
3765         while (idt77252_chain) {
3766                 card = idt77252_chain;
3767                 dev = card->atmdev;
3768                 idt77252_chain = card->next;
3769
3770                 if (dev->phy->stop)
3771                         dev->phy->stop(dev);
3772                 deinit_card(card);
3773                 pci_disable_device(card->pcidev);
3774                 kfree(card);
3775         }
3776
3777         DIPRINTK("idt77252: finished cleanup-module().\n");
3778 }
3779
3780 module_init(idt77252_init);
3781 module_exit(idt77252_exit);
3782
3783 MODULE_LICENSE("GPL");
3784
3785 module_param(vpibits, uint, 0);
3786 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3787 #ifdef CONFIG_ATM_IDT77252_DEBUG
3788 module_param(debug, ulong, 0644);
3789 MODULE_PARM_DESC(debug,   "debug bitmap, see drivers/atm/idt77252.h");
3790 #endif
3791
3792 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3793 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");