drivers/ati_radeon_fb.h

   1 #ifndef __ATI_RADEON_FB_H
   2 #define __ATI_RADEON_FB_H
   3
   4 /***************************************************************
   5  * Most of the definitions here are adapted right from XFree86 *
   6  ***************************************************************/
   7
   8
   9 /*
  10  * Chip families. Must fit in the low 16 bits of a long word
  11  */
  12 enum radeon_family {
  13         CHIP_FAMILY_UNKNOW,
  14         CHIP_FAMILY_LEGACY,
  15         CHIP_FAMILY_RADEON,
  16         CHIP_FAMILY_RV100,
  17         CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
  18         CHIP_FAMILY_RV200,
  19         CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
  20                                  RS250 (IGP 7000) */
  21         CHIP_FAMILY_R200,
  22         CHIP_FAMILY_RV250,
  23         CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
  24         CHIP_FAMILY_RV280,
  25         CHIP_FAMILY_R300,
  26         CHIP_FAMILY_R350,
  27         CHIP_FAMILY_RV350,
  28         CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
  29         CHIP_FAMILY_R420,     /* R420/R423/M18 */
  30         CHIP_FAMILY_LAST,
  31 };
  32
  33 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
  34                                  ((rinfo)->family == CHIP_FAMILY_RV200)  || \
  35                                  ((rinfo)->family == CHIP_FAMILY_RS100)  || \
  36                                  ((rinfo)->family == CHIP_FAMILY_RS200)  || \
  37                                  ((rinfo)->family == CHIP_FAMILY_RV250)  || \
  38                                  ((rinfo)->family == CHIP_FAMILY_RV280)  || \
  39                                  ((rinfo)->family == CHIP_FAMILY_RS300))
  40
  41
  42 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
  43                                 ((rinfo)->family == CHIP_FAMILY_RV350) || \
  44                                 ((rinfo)->family == CHIP_FAMILY_R350)  || \
  45                                 ((rinfo)->family == CHIP_FAMILY_RV380) || \
  46                                 ((rinfo)->family == CHIP_FAMILY_R420))
  47
  48
  49 struct radeonfb_info {
  50         char name[20];
  51
  52         struct pci_device_id    pdev;
  53         u16                     family;
  54
  55         u32                     fb_base_phys;
  56         u32                     mmio_base_phys;
  57
  58         void                    *mmio_base;
  59         void                    *fb_base;
  60
  61         u32                     video_ram;
  62         u32                     mapped_vram;
  63         int                     vram_width;
  64         int                     vram_ddr;
  65
  66         u32                     fb_local_base;
  67 };
  68
  69 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
  70 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
  71 #define INREG16(addr)           readw((rinfo->mmio_base)+addr)
  72 #define OUTREG16(addr,val)      writew(val, (rinfo->mmio_base)+addr)
  73 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
  74 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
  75
  76 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
  77                        u32 val, u32 mask)
  78 {
  79         unsigned int tmp;
  80
  81         tmp = INREG(addr);
  82         tmp &= (mask);
  83         tmp |= (val);
  84         OUTREG(addr, tmp);
  85 }
  86
  87 #define OUTREGP(addr,val,mask)  _OUTREGP(rinfo, addr, val,mask)
  88
  89
  90 /*
  91  * 2D Engine helper routines
  92  */
  93 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
  94 {
  95         int i;
  96
  97         /* initiate flush */
  98         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
  99                 ~RB2D_DC_FLUSH_ALL);
 100
 101         for (i=0; i < 2000000; i++) {
 102                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 103                         return;
 104                 udelay(1);
 105         }
 106         printf("radeonfb: Flush Timeout !\n");
 107 }
 108
 109
 110 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
 111 {
 112         int i;
 113
 114         for (i=0; i<2000000; i++) {
 115                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 116                         return;
 117                 udelay(1);
 118         }
 119         printf("radeonfb: FIFO Timeout !\n");
 120 }
 121
 122
 123 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
 124 {
 125         int i;
 126
 127         /* ensure FIFO is empty before waiting for idle */
 128         _radeon_fifo_wait (rinfo, 64);
 129
 130         for (i=0; i<2000000; i++) {
 131                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 132                         radeon_engine_flush (rinfo);
 133                         return;
 134                 }
 135                 udelay(1);
 136         }
 137         printf("radeonfb: Idle Timeout !\n");
 138 }
 139
 140
 141 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 142 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 143 #define radeon_msleep(ms)               _radeon_msleep(rinfo,ms)
 144
 145 /*
 146  * This structure contains the various registers manipulated by this
 147  * driver for setting or restoring a mode. It's mostly copied from
 148  * XFree's RADEONSaveRec structure. A few chip settings might still be
 149  * tweaked without beeing reflected or saved in these registers though
 150  */
 151 struct radeon_regs {
 152         /* Common registers */
 153         u32             ovr_clr;
 154         u32             ovr_wid_left_right;
 155         u32             ovr_wid_top_bottom;
 156         u32             ov0_scale_cntl;
 157         u32             mpp_tb_config;
 158         u32             mpp_gp_config;
 159         u32             subpic_cntl;
 160         u32             viph_control;
 161         u32             i2c_cntl_1;
 162         u32             gen_int_cntl;
 163         u32             cap0_trig_cntl;
 164         u32             cap1_trig_cntl;
 165         u32             bus_cntl;
 166         u32             surface_cntl;
 167         u32             bios_5_scratch;
 168
 169         /* Other registers to save for VT switches or driver load/unload */
 170         u32             dp_datatype;
 171         u32             rbbm_soft_reset;
 172         u32             clock_cntl_index;
 173         u32             amcgpio_en_reg;
 174         u32             amcgpio_mask;
 175
 176         /* Surface/tiling registers */
 177         u32             surf_lower_bound[8];
 178         u32             surf_upper_bound[8];
 179         u32             surf_info[8];
 180
 181         /* CRTC registers */
 182         u32             crtc_gen_cntl;
 183         u32             crtc_ext_cntl;
 184         u32             dac_cntl;
 185         u32             crtc_h_total_disp;
 186         u32             crtc_h_sync_strt_wid;
 187         u32             crtc_v_total_disp;
 188         u32             crtc_v_sync_strt_wid;
 189         u32             crtc_offset;
 190         u32             crtc_offset_cntl;
 191         u32             crtc_pitch;
 192         u32             disp_merge_cntl;
 193         u32             grph_buffer_cntl;
 194         u32             crtc_more_cntl;
 195
 196         /* CRTC2 registers */
 197         u32             crtc2_gen_cntl;
 198         u32             dac2_cntl;
 199         u32             disp_output_cntl;
 200         u32             disp_hw_debug;
 201         u32             disp2_merge_cntl;
 202         u32             grph2_buffer_cntl;
 203         u32             crtc2_h_total_disp;
 204         u32             crtc2_h_sync_strt_wid;
 205         u32             crtc2_v_total_disp;
 206         u32             crtc2_v_sync_strt_wid;
 207         u32             crtc2_offset;
 208         u32             crtc2_offset_cntl;
 209         u32             crtc2_pitch;
 210
 211         /* Flat panel regs */
 212         u32             fp_crtc_h_total_disp;
 213         u32             fp_crtc_v_total_disp;
 214         u32             fp_gen_cntl;
 215         u32             fp2_gen_cntl;
 216         u32             fp_h_sync_strt_wid;
 217         u32             fp2_h_sync_strt_wid;
 218         u32             fp_horz_stretch;
 219         u32             fp_panel_cntl;
 220         u32             fp_v_sync_strt_wid;
 221         u32             fp2_v_sync_strt_wid;
 222         u32             fp_vert_stretch;
 223         u32             lvds_gen_cntl;
 224         u32             lvds_pll_cntl;
 225         u32             tmds_crc;
 226         u32             tmds_transmitter_cntl;
 227
 228         /* Computed values for PLL */
 229         u32             dot_clock_freq;
 230         int             feedback_div;
 231         int             post_div;
 232
 233         /* PLL registers */
 234         u32             ppll_div_3;
 235         u32             ppll_ref_div;
 236         u32             vclk_ecp_cntl;
 237         u32             clk_cntl_index;
 238
 239         /* Computed values for PLL2 */
 240         u32             dot_clock_freq_2;
 241         int             feedback_div_2;
 242         int             post_div_2;
 243
 244         /* PLL2 registers */
 245         u32             p2pll_ref_div;
 246         u32             p2pll_div_0;
 247         u32             htotal_cntl2;
 248
 249         /* Palette */
 250         int             palette_valid;
 251 };
 252
 253 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
 254 {
 255         u32 data;
 256
 257         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 258         //radeon_pll_errata_after_index(rinfo);
 259         data = INREG(CLOCK_CNTL_DATA);
 260         //radeon_pll_errata_after_data(rinfo);
 261         return data;
 262 }
 263
 264 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
 265                             u32 val)
 266 {
 267
 268         OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
 269         //radeon_pll_errata_after_index(rinfo);
 270         OUTREG(CLOCK_CNTL_DATA, val);
 271         //radeon_pll_errata_after_data(rinfo);
 272 }
 273
 274
 275 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
 276                              u32 val, u32 mask)
 277 {
 278         unsigned int tmp;
 279
 280         tmp  = __INPLL(rinfo, index);
 281         tmp &= (mask);
 282         tmp |= (val);
 283         __OUTPLL(rinfo, index, tmp);
 284 }
 285
 286
 287 #define INPLL(addr)                     __INPLL(rinfo, addr)
 288 #define OUTPLL(index, val)              __OUTPLL(rinfo, index, val)
 289 #define OUTPLLP(index, val, mask)       __OUTPLLP(rinfo, index, val, mask)
 290
 291
 292
 293 #endif