1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
4 * Author: Tor Krill <tor@excito.com>
6 * This is a driver for Silicon Image sil3114 sata chip modelled on
16 #include <asm/byteorder.h>
21 #include "sata_sil3114.h"
23 /* Convert sectorsize to wordsize */
24 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
27 u8 sil3114_spin_up (int num);
28 u8 sil3114_spin_down (int num);
29 static int sata_bus_softreset (int num);
30 static void sata_identify (int num, int dev);
31 static u8 check_power_mode (int num);
32 static void sata_port (struct sata_ioports *ioport);
33 static void set_Feature_cmd (int num, int dev);
34 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
35 unsigned int max, u8 usealtstatus);
36 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
37 static void msleep (int count);
39 static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
41 static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
43 static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
46 __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
50 static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
53 *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
58 static int sata_bus_softreset (int num)
62 port[num].dev_mask = 1;
64 port[num].ctl_reg = 0x08; /*Default value of control reg */
65 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
67 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
69 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
71 /* spec mandates ">= 2ms" before checking status.
72 * We wait 150ms, because that was the magic delay used for
73 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
74 * between when the ATA command register is written, and then
75 * status is checked. Because waiting for "a while" before
76 * checking status is fine, post SRST, we perform this magic
80 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
81 while ((status & ATA_BUSY)) {
83 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
86 if (status & ATA_BUSY) {
87 printf ("ata%u is slow to respond,plz be patient\n", num);
90 while ((status & ATA_BUSY)) {
92 status = sata_chk_status (&port[num].ioaddr, 0);
95 if (status & ATA_BUSY) {
96 printf ("ata%u failed to respond : ", num);
97 printf ("bus reset failed\n");
98 port[num].dev_mask = 0;
104 static void sata_identify (int num, int dev)
106 u8 cmd = 0, status = 0, devno = num;
107 u16 iobuf[ATA_SECTOR_WORDS];
110 memset (iobuf, 0, sizeof (iobuf));
112 if (!(port[num].dev_mask & 0x01)) {
113 printf ("dev%d is not present on port#%d\n", dev, num);
117 debug ("port=%d dev=%d\n", num, dev);
120 cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
121 writeb (cmd, port[num].ioaddr.command_addr);
122 readb (port[num].ioaddr.altstatus_addr);
125 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
126 if (status & ATA_ERR) {
127 printf ("\ndevice not responding\n");
128 port[num].dev_mask &= ~0x01;
132 input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
134 ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
136 debug ("Specific config: %x\n", iobuf[2]);
138 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
139 if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
140 debug ("ata%u: no dma/lba\n", num);
145 n_sectors = ata_id_n_sectors (iobuf);
147 if (n_sectors == 0) {
148 port[num].dev_mask &= ~0x01;
151 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
152 ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
153 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
154 ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
155 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
156 ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
158 /* TODO - atm we asume harddisk ie not removable */
159 sata_dev_desc[devno].removable = 0;
161 sata_dev_desc[devno].lba = (u32) n_sectors;
162 debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
165 if (iobuf[83] & (1 << 10)) {
166 sata_dev_desc[devno].lba48 = 1;
168 sata_dev_desc[devno].lba48 = 0;
173 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
174 sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
175 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
178 static void set_Feature_cmd (int num, int dev)
182 if (!(port[num].dev_mask & 0x01)) {
183 debug ("dev%d is not present on port#%d\n", dev, num);
187 writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
188 writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
189 writeb (0, port[num].ioaddr.lbal_addr);
190 writeb (0, port[num].ioaddr.lbam_addr);
191 writeb (0, port[num].ioaddr.lbah_addr);
193 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
194 writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
199 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
200 if ((status & (ATA_BUSY | ATA_ERR))) {
201 printf ("Error : status 0x%02x\n", status);
202 port[num].dev_mask &= ~0x01;
206 u8 sil3114_spin_down (int num)
210 debug ("Spin down disk\n");
212 if (!(port[num].dev_mask & 0x01)) {
213 debug ("Device ata%d is not present\n", num);
217 if ((status = check_power_mode (num)) == 0x00) {
218 debug ("Already in standby\n");
222 if (status == 0x01) {
223 printf ("Failed to check power mode on ata%d\n", num);
227 if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
228 printf ("Device ata%d not ready\n", num);
232 writeb (0x00, port[num].ioaddr.feature_addr);
234 writeb (0x00, port[num].ioaddr.nsect_addr);
235 writeb (0x00, port[num].ioaddr.lbal_addr);
236 writeb (0x00, port[num].ioaddr.lbam_addr);
237 writeb (0x00, port[num].ioaddr.lbah_addr);
239 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
240 writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
242 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
243 if ((status & (ATA_BUSY | ATA_ERR))) {
244 printf ("Error waiting for disk spin down: status 0x%02x\n",
246 port[num].dev_mask &= ~0x01;
252 u8 sil3114_spin_up (int num)
256 debug ("Spin up disk\n");
258 if (!(port[num].dev_mask & 0x01)) {
259 debug ("Device ata%d is not present\n", num);
263 if ((status = check_power_mode (num)) != 0x00) {
264 if (status == 0x01) {
265 printf ("Failed to check power mode on ata%d\n", num);
268 /* should be up and running already */
273 if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
274 printf ("Device ata%d not ready\n", num);
278 debug ("Stautus of device check: %d\n", status);
280 writeb (0x00, port[num].ioaddr.feature_addr);
282 writeb (0x00, port[num].ioaddr.nsect_addr);
283 writeb (0x00, port[num].ioaddr.lbal_addr);
284 writeb (0x00, port[num].ioaddr.lbam_addr);
285 writeb (0x00, port[num].ioaddr.lbah_addr);
287 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
288 writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
290 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
291 if ((status & (ATA_BUSY | ATA_ERR))) {
292 printf ("Error waiting for disk spin up: status 0x%02x\n",
294 port[num].dev_mask &= ~0x01;
298 /* Wait for disk to enter Active state */
301 status = check_power_mode (num);
302 } while ((status == 0x00) || (status == 0x80));
304 if (status == 0x01) {
305 printf ("Falied waiting for disk to spin up\n");
312 /* Return value is not the usual here
313 * 0x00 - Device stand by
314 * 0x01 - Operation failed
316 * 0xff - Device active
318 static u8 check_power_mode (int num)
322 if (!(port[num].dev_mask & 0x01)) {
323 debug ("Device ata%d is not present\n", num);
327 if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
328 printf ("Device ata%d not ready\n", num);
332 writeb (0, port[num].ioaddr.feature_addr);
333 writeb (0, port[num].ioaddr.nsect_addr);
334 writeb (0, port[num].ioaddr.lbal_addr);
335 writeb (0, port[num].ioaddr.lbam_addr);
336 writeb (0, port[num].ioaddr.lbah_addr);
338 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
339 writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
341 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
342 if ((status & (ATA_BUSY | ATA_ERR))) {
344 ("Error waiting for check power mode complete : status 0x%02x\n",
346 port[num].dev_mask &= ~0x01;
349 res = readb (port[num].ioaddr.nsect_addr);
350 debug ("Check powermode: %d\n", res);
355 static void sata_port (struct sata_ioports *ioport)
357 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
358 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
359 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
360 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
361 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
362 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
363 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
364 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
365 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
366 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
369 static u8 wait_for_irq (int num, unsigned int max)
372 u32 port = iobase[5];
375 port += VND_TF_CNST_CH0;
378 port += VND_TF_CNST_CH1;
381 port += VND_TF_CNST_CH2;
384 port += VND_TF_CNST_CH3;
391 if (readl (port) & VND_TF_CNST_INTST) {
401 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
402 unsigned int max, u8 usealtstatus)
407 if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
412 } while ((status & bits) && (max > 0));
417 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
420 return readb (ioaddr->status_addr);
422 return readb (ioaddr->altstatus_addr);
426 static void msleep (int count)
430 for (i = 0; i < count; i++)
434 /* Read up to 255 sectors
436 * Returns sectors read
438 static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
444 u64 blknr = (u64) block;
446 if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
447 printf ("Device ata%d not ready\n", device);
451 /* Set up transfer */
454 /* write high bits */
455 writeb (0, port[device].ioaddr.nsect_addr);
456 writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
457 writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
458 writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
461 writeb (blkcnt, port[device].ioaddr.nsect_addr);
462 writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
463 writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
464 writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
468 writeb (ATA_LBA, port[device].ioaddr.device_addr);
469 writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
473 writeb (ATA_LBA | ((blknr >> 24) & 0xF),
474 port[device].ioaddr.device_addr);
475 writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
478 status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
480 if (status & ATA_BUSY) {
483 printf ("Device %d not responding status %d\n", device, status);
484 err = readb (port[device].ioaddr.error_addr);
485 printf ("Error reg = 0x%x\n", err);
491 if (wait_for_irq (device, 500)) {
492 printf ("ata%u irq failed\n", device);
496 status = sata_chk_status (&port[device].ioaddr, 0);
497 if (status & ATA_ERR) {
498 printf ("ata%u error %d\n", device,
499 readb (port[device].ioaddr.error_addr));
502 /* Read one sector */
503 input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
504 buff += ATA_SECTOR_WORDS;
511 ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
514 u16 *buffer = (u16 *) buff;
516 u64 blknr = (u64) block;
517 unsigned char lba48 = 0;
520 if (blknr > 0xfffffff) {
521 if (!sata_dev_desc[device].lba48) {
522 printf ("Drive doesn't support 48-bit addressing\n");
525 /* more than 28 bits used, use 48bit mode */
538 status = do_one_read (device, blknr, sread, buffer, lba48);
539 if (status != sread) {
540 printf ("Read failed\n");
547 buffer += sread * ATA_SECTOR_WORDS;
552 ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
555 u16 *buffer = (u16 *) buff;
556 unsigned char status = 0, num = 0;
557 u64 blknr = (u64) block;
559 unsigned char lba48 = 0;
561 if (blknr > 0xfffffff) {
562 if (!sata_dev_desc[device].lba48) {
563 printf ("Drive doesn't support 48-bit addressing\n");
566 /* more than 28 bits used, use 48bit mode */
573 while (blkcnt-- > 0) {
574 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
575 if (status & ATA_BUSY) {
576 printf ("ata%u failed to respond\n", port[num].port_no);
581 /* write high bits */
582 writeb (0, port[num].ioaddr.nsect_addr);
583 writeb ((blknr >> 24) & 0xFF,
584 port[num].ioaddr.lbal_addr);
585 writeb ((blknr >> 32) & 0xFF,
586 port[num].ioaddr.lbam_addr);
587 writeb ((blknr >> 40) & 0xFF,
588 port[num].ioaddr.lbah_addr);
591 writeb (1, port[num].ioaddr.nsect_addr);
592 writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
593 writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
594 writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
597 writeb (ATA_LBA, port[num].ioaddr.device_addr);
598 writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
602 writeb (ATA_LBA | ((blknr >> 24) & 0xF),
603 port[num].ioaddr.device_addr);
604 writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
608 /*may take up to 4 sec */
609 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
610 if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
611 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
612 device, (ulong) blknr, status);
616 output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
617 readb (port[num].ioaddr.altstatus_addr);
622 buffer += ATA_SECTOR_WORDS;
627 /* Driver implementation */
628 static u8 sil_get_device_cache_line (pci_dev_t pdev)
631 pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
635 int init_sata (int dev)
637 static u8 init_done = 0;
650 if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
655 /* Read out all BARs, even though we only use MMIO from BAR5 */
656 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
657 pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
658 pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
659 pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
660 pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
661 pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
663 if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
664 (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
665 (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
666 printf ("Error no base addr for SATA controller\n");
671 /* mask off unused bits */
672 iobase[0] &= 0xfffffffc;
673 iobase[1] &= 0xfffffff8;
674 iobase[2] &= 0xfffffffc;
675 iobase[3] &= 0xfffffff8;
676 iobase[4] &= 0xfffffff0;
677 iobase[5] &= 0xfffffc00;
679 /* from sata_sil in Linux kernel */
680 cls = sil_get_device_cache_line (devno);
683 cls++; /* cls = (line_size/8)+1 */
684 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
685 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
686 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
687 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
689 printf ("Cache line not set. Driver may not function\n");
692 /* Enable operation */
693 pci_read_config_word (devno, PCI_COMMAND, &cmd);
694 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
695 pci_write_config_word (devno, PCI_COMMAND, cmd);
697 /* Disable interrupt usage */
698 pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
699 sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
700 pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
706 int reset_sata(int dev)
711 /* Check if device is connected to port */
712 int sata_bus_probe (int portno)
714 u32 port = iobase[5];
718 port += VND_SSTATUS_CH0;
721 port += VND_SSTATUS_CH1;
724 port += VND_SSTATUS_CH2;
727 port += VND_SSTATUS_CH3;
733 if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
740 int sata_phy_reset (int portno)
742 u32 port = iobase[5];
746 port += VND_SCONTROL_CH0;
749 port += VND_SCONTROL_CH1;
752 port += VND_SCONTROL_CH2;
755 port += VND_SCONTROL_CH3;
761 writel (val | SATA_SC_DET_RST, port);
763 writel (val & ~SATA_SC_DET_RST, port);
767 int scan_sata (int dev)
769 /* A bit brain dead, but the code has a legacy */
773 port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
774 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
775 (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
776 port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
778 #if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
781 port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
782 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
783 (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
784 port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
786 #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
789 port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
790 port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
791 (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
792 port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
794 #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
797 port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
798 port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
799 (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
800 port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
804 printf ("Tried to scan unknown port: ata%d\n", dev);
808 /* Initialize other registers */
809 sata_port (&port[dev].ioaddr);
811 /* Check for attached device */
812 if (!sata_bus_probe (dev)) {
813 port[dev].port_state = 0;
814 debug ("SATA#%d port is not present\n", dev);
816 debug ("SATA#%d port is present\n", dev);
817 if (sata_bus_softreset (dev)) {
818 /* soft reset failed, try a hard one */
819 sata_phy_reset (dev);
820 if (sata_bus_softreset (dev)) {
821 port[dev].port_state = 0;
823 port[dev].port_state = 1;
826 port[dev].port_state = 1;
829 if (port[dev].port_state == 1) {
830 /* Probe device and set xfer mode */
831 sata_identify (dev, 0);
832 set_Feature_cmd (dev, 0);