drivers/ata/sata_sil.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  * Author: Tang Yuantian <b29983@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <pci.h>
  10 #include <command.h>
  11 #include <asm/byteorder.h>
  12 #include <malloc.h>
  13 #include <asm/io.h>
  14 #include <fis.h>
  15 #include <sata.h>
  16 #include <libata.h>
  17 #include <sata.h>
  18
  19 #if CONFIG_IS_ENABLED(BLK)
  20 #include <dm.h>
  21 #include <blk.h>
  22 #endif
  23
  24 #include "sata_sil.h"
  25
  26 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  27
  28 /* just compatible ahci_ops */
  29 struct sil_ops {
  30         int *rev0;
  31         int *rev1;
  32         int (*scan)(struct udevice *dev);
  33 };
  34
  35 static struct sata_info sata_info;
  36
  37 static struct pci_device_id supported[] = {
  38         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
  39         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
  40         { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
  41         {}
  42 };
  43
  44 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
  45 {
  46         printf("Status FIS dump:\n");
  47         printf("fis_type:               %02x\n", s->fis_type);
  48         printf("pm_port_i:              %02x\n", s->pm_port_i);
  49         printf("status:                 %02x\n", s->status);
  50         printf("error:                  %02x\n", s->error);
  51         printf("lba_low:                %02x\n", s->lba_low);
  52         printf("lba_mid:                %02x\n", s->lba_mid);
  53         printf("lba_high:               %02x\n", s->lba_high);
  54         printf("device:                 %02x\n", s->device);
  55         printf("lba_low_exp:            %02x\n", s->lba_low_exp);
  56         printf("lba_mid_exp:            %02x\n", s->lba_mid_exp);
  57         printf("lba_high_exp:           %02x\n", s->lba_high_exp);
  58         printf("res1:                   %02x\n", s->res1);
  59         printf("sector_count:           %02x\n", s->sector_count);
  60         printf("sector_count_exp:       %02x\n", s->sector_count_exp);
  61 }
  62
  63 static const char *sata_spd_string(unsigned int speed)
  64 {
  65         static const char * const spd_str[] = {
  66                 "1.5 Gbps",
  67                 "3.0 Gbps",
  68                 "6.0 Gbps",
  69         };
  70
  71         if ((speed - 1) > 2)
  72                 return "<unknown>";
  73
  74         return spd_str[speed - 1];
  75 }
  76
  77 static u32 ata_wait_register(void *reg, u32 mask,
  78                          u32 val, int timeout_msec)
  79 {
  80         u32 tmp;
  81
  82         tmp = readl(reg);
  83         while ((tmp & mask) == val && timeout_msec > 0) {
  84                 mdelay(1);
  85                 timeout_msec--;
  86                 tmp = readl(reg);
  87         }
  88
  89         return tmp;
  90 }
  91
  92 static void sil_config_port(void *port)
  93 {
  94         /* configure IRQ WoC */
  95         writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
  96
  97         /* zero error counters. */
  98         writew(0x8000, port + PORT_DECODE_ERR_THRESH);
  99         writew(0x8000, port + PORT_CRC_ERR_THRESH);
 100         writew(0x8000, port + PORT_HSHK_ERR_THRESH);
 101         writew(0x0000, port + PORT_DECODE_ERR_CNT);
 102         writew(0x0000, port + PORT_CRC_ERR_CNT);
 103         writew(0x0000, port + PORT_HSHK_ERR_CNT);
 104
 105         /* always use 64bit activation */
 106         writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
 107
 108         /* clear port multiplier enable and resume bits */
 109         writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
 110 }
 111
 112 static int sil_init_port(void *port)
 113 {
 114         u32 tmp;
 115
 116         writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
 117         ata_wait_register(port + PORT_CTRL_STAT,
 118                           PORT_CS_INIT, PORT_CS_INIT, 100);
 119         tmp = ata_wait_register(port + PORT_CTRL_STAT,
 120                                 PORT_CS_RDY, 0, 100);
 121
 122         if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
 123                 return 1;
 124
 125         return 0;
 126 }
 127
 128 static void sil_read_fis(struct sil_sata *sata, int tag,
 129                          struct sata_fis_d2h *fis)
 130 {
 131         void *port = sata->port;
 132         struct sil_prb *prb;
 133         int i;
 134         u32 *src, *dst;
 135
 136         prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
 137         src = (u32 *)&prb->fis;
 138         dst = (u32 *)fis;
 139         for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
 140                 *dst++ = readl(src++);
 141 }
 142
 143 static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
 144                         int tag)
 145 {
 146         void *port = sata->port;
 147         u64 paddr = virt_to_bus(sata->devno, pcmd);
 148         u32 irq_mask, irq_stat;
 149         int rc;
 150
 151         writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
 152
 153         /* better to add momery barrior here */
 154         writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
 155         writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
 156
 157         irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
 158         irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
 159                         0, 10000);
 160
 161         /* clear IRQs */
 162         writel(irq_mask, port + PORT_IRQ_STAT);
 163         irq_stat >>= PORT_IRQ_RAW_SHIFT;
 164
 165         if (irq_stat & PORT_IRQ_COMPLETE)
 166                 rc = 0;
 167         else {
 168                 /* force port into known state */
 169                 sil_init_port(port);
 170                 if (irq_stat & PORT_IRQ_ERROR)
 171                         rc = 1; /* error */
 172                 else
 173                         rc = 2; /* busy */
 174         }
 175
 176         return rc;
 177 }
 178
 179 static int sil_cmd_set_feature(struct sil_sata *sata)
 180 {
 181         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 182         struct sata_fis_d2h fis;
 183         u8 udma_cap;
 184         int ret;
 185
 186         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 187         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 188         pcmd->prb.fis.pm_port_c = (1 << 7);
 189         pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
 190         pcmd->prb.fis.features = SETFEATURES_XFER;
 191
 192         /* First check the device capablity */
 193         udma_cap = (u8)(sata->udma & 0xff);
 194         debug("udma_cap %02x\n", udma_cap);
 195
 196         if (udma_cap == ATA_UDMA6)
 197                 pcmd->prb.fis.sector_count = XFER_UDMA_6;
 198         if (udma_cap == ATA_UDMA5)
 199                 pcmd->prb.fis.sector_count = XFER_UDMA_5;
 200         if (udma_cap == ATA_UDMA4)
 201                 pcmd->prb.fis.sector_count = XFER_UDMA_4;
 202         if (udma_cap == ATA_UDMA3)
 203                 pcmd->prb.fis.sector_count = XFER_UDMA_3;
 204
 205         ret = sil_exec_cmd(sata, pcmd, 0);
 206         if (ret) {
 207                 sil_read_fis(sata, 0, &fis);
 208                 printf("Err: exe cmd(0x%x).\n",
 209                                 readl(sata->port + PORT_SERROR));
 210                 sil_sata_dump_fis(&fis);
 211                 return 1;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
 218 {
 219         if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
 220                 sata->wcache = 1;
 221         if (ata_id_has_flush(id))
 222                 sata->flush = 1;
 223         if (ata_id_has_flush_ext(id))
 224                 sata->flush_ext = 1;
 225 }
 226
 227 static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
 228 {
 229 #ifdef CONFIG_LBA48
 230         /* Check if support LBA48 */
 231         if (ata_id_has_lba48(id)) {
 232                 sata->lba48 = 1;
 233                 debug("Device supports LBA48\n");
 234         } else {
 235                 debug("Device supports LBA28\n");
 236         }
 237 #endif
 238
 239         sil_sata_init_wcache(sata, id);
 240         sil_cmd_set_feature(sata);
 241 }
 242
 243 static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
 244 {
 245         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 246         struct sata_fis_d2h fis;
 247         int ret;
 248
 249         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 250         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 251         pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 252         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 253         pcmd->prb.fis.pm_port_c = (1 << 7);
 254         pcmd->prb.fis.command = ATA_CMD_ID_ATA;
 255         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
 256         pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
 257         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 258
 259         ret = sil_exec_cmd(sata, pcmd, 0);
 260         if (ret) {
 261                 sil_read_fis(sata, 0, &fis);
 262                 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
 263                 sil_sata_dump_fis(&fis);
 264                 return 1;
 265         }
 266         ata_swap_buf_le16(id, ATA_ID_WORDS);
 267
 268         return 0;
 269 }
 270
 271 static int sil_cmd_soft_reset(struct sil_sata *sata)
 272 {
 273         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 274         struct sata_fis_d2h fis;
 275         void *port = sata->port;
 276         int ret;
 277
 278         /* put the port into known state */
 279         if (sil_init_port(port)) {
 280                 printf("SRST: port %d not ready\n", sata->id);
 281                 return 1;
 282         }
 283
 284         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 285
 286         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
 287         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 288         pcmd->prb.fis.pm_port_c = 0xf;
 289
 290         ret = sil_exec_cmd(sata, &cmdb, 0);
 291         if (ret) {
 292                 sil_read_fis(sata, 0, &fis);
 293                 printf("SRST cmd error.\n");
 294                 sil_sata_dump_fis(&fis);
 295                 return 1;
 296         }
 297
 298         return 0;
 299 }
 300
 301 static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
 302                              u8 *buffer, int is_write)
 303 {
 304         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 305         struct sata_fis_d2h fis;
 306         u64 block;
 307         int ret;
 308
 309         block = (u64)start;
 310         memset(pcmd, 0, sizeof(struct sil_cmd_block));
 311         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 312         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 313         pcmd->prb.fis.pm_port_c = (1 << 7);
 314         if (is_write) {
 315                 pcmd->prb.fis.command = ATA_CMD_WRITE;
 316                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
 317         } else {
 318                 pcmd->prb.fis.command = ATA_CMD_READ;
 319                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 320         }
 321
 322         pcmd->prb.fis.device = ATA_LBA;
 323         pcmd->prb.fis.device |= (block >> 24) & 0xf;
 324         pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
 325         pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
 326         pcmd->prb.fis.lba_low = block & 0xff;
 327         pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
 328
 329         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
 330         pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
 331         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 332
 333         ret = sil_exec_cmd(sata, pcmd, 0);
 334         if (ret) {
 335                 sil_read_fis(sata, 0, &fis);
 336                 printf("Err: rw cmd(0x%08x).\n",
 337                                 readl(sata->port + PORT_SERROR));
 338                 sil_sata_dump_fis(&fis);
 339                 return 1;
 340         }
 341
 342         return blkcnt;
 343 }
 344
 345 static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
 346                                  ulong blkcnt, u8 *buffer, int is_write)
 347 {
 348         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 349         struct sata_fis_d2h fis;
 350         u64 block;
 351         int ret;
 352
 353         block = (u64)start;
 354         memset(pcmd, 0, sizeof(struct sil_cmd_block));
 355         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 356         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 357         pcmd->prb.fis.pm_port_c = (1 << 7);
 358         if (is_write) {
 359                 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
 360                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
 361         } else {
 362                 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
 363                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 364         }
 365
 366         pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
 367         pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
 368         pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
 369         pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
 370         pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
 371         pcmd->prb.fis.lba_low = block & 0xff;
 372         pcmd->prb.fis.device = ATA_LBA;
 373         pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
 374         pcmd->prb.fis.sector_count = blkcnt & 0xff;
 375
 376         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
 377         pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
 378         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 379
 380         ret = sil_exec_cmd(sata, pcmd, 0);
 381         if (ret) {
 382                 sil_read_fis(sata, 0, &fis);
 383                 printf("Err: rw ext cmd(0x%08x).\n",
 384                                 readl(sata->port + PORT_SERROR));
 385                 sil_sata_dump_fis(&fis);
 386                 return 1;
 387         }
 388
 389         return blkcnt;
 390 }
 391
 392 static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
 393                                lbaint_t blkcnt, const void *buffer,
 394                                int is_write)
 395 {
 396         ulong start, blks, max_blks;
 397         u8 *addr;
 398
 399         start = blknr;
 400         blks = blkcnt;
 401         addr = (u8 *)buffer;
 402
 403         max_blks = ATA_MAX_SECTORS;
 404         do {
 405                 if (blks > max_blks) {
 406                         sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
 407                         start += max_blks;
 408                         blks -= max_blks;
 409                         addr += ATA_SECT_SIZE * max_blks;
 410                 } else {
 411                         sil_sata_rw_cmd(sata, start, blks, addr, is_write);
 412                         start += blks;
 413                         blks = 0;
 414                         addr += ATA_SECT_SIZE * blks;
 415                 }
 416         } while (blks != 0);
 417
 418         return blkcnt;
 419 }
 420
 421 static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
 422                                lbaint_t blkcnt, const void *buffer,
 423                                int is_write)
 424 {
 425         ulong start, blks, max_blks;
 426         u8 *addr;
 427
 428         start = blknr;
 429         blks = blkcnt;
 430         addr = (u8 *)buffer;
 431
 432         max_blks = ATA_MAX_SECTORS_LBA48;
 433         do {
 434                 if (blks > max_blks) {
 435                         sil_sata_rw_cmd_ext(sata, start, max_blks,
 436                                             addr, is_write);
 437                         start += max_blks;
 438                         blks -= max_blks;
 439                         addr += ATA_SECT_SIZE * max_blks;
 440                 } else {
 441                         sil_sata_rw_cmd_ext(sata, start, blks,
 442                                             addr, is_write);
 443                         start += blks;
 444                         blks = 0;
 445                         addr += ATA_SECT_SIZE * blks;
 446                 }
 447         } while (blks != 0);
 448
 449         return blkcnt;
 450 }
 451
 452 static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
 453 {
 454         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 455
 456         memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
 457         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 458         pcmd->prb.fis.pm_port_c = (1 << 7);
 459         pcmd->prb.fis.command = ATA_CMD_FLUSH;
 460
 461         sil_exec_cmd(sata, pcmd, 0);
 462 }
 463
 464 static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
 465 {
 466         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 467
 468         memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
 469         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 470         pcmd->prb.fis.pm_port_c = (1 << 7);
 471         pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
 472
 473         sil_exec_cmd(sata, pcmd, 0);
 474 }
 475
 476 /*
 477  * SATA interface between low level driver and command layer
 478  */
 479 #if !CONFIG_IS_ENABLED(BLK)
 480 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
 481 {
 482         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 483 #else
 484 static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 485                        void *buffer)
 486 {
 487         struct sil_sata_priv *priv = dev_get_platdata(dev);
 488         int port_number = priv->port_num;
 489         struct sil_sata *sata = priv->sil_sata_desc[port_number];
 490 #endif
 491         ulong rc;
 492
 493         if (sata->lba48)
 494                 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
 495         else
 496                 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
 497
 498         return rc;
 499 }
 500
 501 /*
 502  * SATA interface between low level driver and command layer
 503  */
 504 #if !CONFIG_IS_ENABLED(BLK)
 505 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
 506 {
 507         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 508 #else
 509 ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 510                  const void *buffer)
 511 {
 512         struct sil_sata_priv *priv = dev_get_platdata(dev);
 513         int port_number = priv->port_num;
 514         struct sil_sata *sata = priv->sil_sata_desc[port_number];
 515 #endif
 516         ulong rc;
 517
 518         if (sata->lba48) {
 519                 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
 520                 if (sata->wcache && sata->flush_ext)
 521                         sil_sata_cmd_flush_cache_ext(sata);
 522         } else {
 523                 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
 524                 if (sata->wcache && sata->flush)
 525                         sil_sata_cmd_flush_cache(sata);
 526         }
 527
 528         return rc;
 529 }
 530
 531 #if !CONFIG_IS_ENABLED(BLK)
 532 static int sil_init_sata(int dev)
 533 {
 534 #else
 535 static int sil_init_sata(struct udevice *uc_dev, int dev)
 536 {
 537         struct sil_sata_priv *priv = dev_get_platdata(uc_dev);
 538 #endif
 539         struct sil_sata *sata;
 540         void *port;
 541         u32 tmp;
 542         int cnt;
 543
 544         printf("SATA#%d:\n", dev);
 545
 546         port = (void *)sata_info.iobase[1] +
 547                 PORT_REGS_SIZE * (dev - sata_info.portbase);
 548
 549         /* Initial PHY setting */
 550         writel(0x20c, port + PORT_PHY_CFG);
 551
 552         /* clear port RST */
 553         tmp = readl(port + PORT_CTRL_STAT);
 554         if (tmp & PORT_CS_PORT_RST) {
 555                 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
 556                 tmp = ata_wait_register(port + PORT_CTRL_STAT,
 557                                 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
 558                 if (tmp & PORT_CS_PORT_RST)
 559                         printf("Err: Failed to clear port RST\n");
 560         }
 561
 562         /* Check if device is present */
 563         for (cnt = 0; cnt < 100; cnt++) {
 564                 tmp = readl(port + PORT_SSTATUS);
 565                 if ((tmp & 0xF) == 0x3)
 566                         break;
 567                 mdelay(1);
 568         }
 569
 570         tmp = readl(port + PORT_SSTATUS);
 571         if ((tmp & 0xf) != 0x3) {
 572                 printf("        (No RDY)\n");
 573                 return 1;
 574         }
 575
 576         /* Wait for port ready */
 577         tmp = ata_wait_register(port + PORT_CTRL_STAT,
 578                                 PORT_CS_RDY, PORT_CS_RDY, 100);
 579         if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
 580                 printf("%d port not ready.\n", dev);
 581                 return 1;
 582         }
 583
 584         /* configure port */
 585         sil_config_port(port);
 586
 587         /* Reset port */
 588         writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
 589         readl(port + PORT_CTRL_STAT);
 590         tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
 591                                 PORT_CS_DEV_RST, 100);
 592         if (tmp & PORT_CS_DEV_RST) {
 593                 printf("%d port reset failed.\n", dev);
 594                 return 1;
 595         }
 596
 597         sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
 598         if (!sata) {
 599                 printf("%d no memory.\n", dev);
 600                 return 1;
 601         }
 602         memset((void *)sata, 0, sizeof(struct sil_sata));
 603
 604         /* Save the private struct to block device struct */
 605 #if !CONFIG_IS_ENABLED(BLK)
 606         sata_dev_desc[dev].priv = (void *)sata;
 607 #else
 608         priv->sil_sata_desc[dev] = sata;
 609         priv->port_num = dev;
 610 #endif
 611         sata->id = dev;
 612         sata->port = port;
 613         sata->devno = sata_info.devno;
 614         sprintf(sata->name, "SATA#%d", dev);
 615         sil_cmd_soft_reset(sata);
 616         tmp = readl(port + PORT_SSTATUS);
 617         tmp = (tmp >> 4) & 0xf;
 618         printf("        (%s)\n", sata_spd_string(tmp));
 619
 620         return 0;
 621 }
 622
 623 #if !CONFIG_IS_ENABLED(BLK)
 624 /*
 625  * SATA interface between low level driver and command layer
 626  */
 627 int init_sata(int dev)
 628 {
 629         static int init_done, idx;
 630         pci_dev_t devno;
 631         u16 word;
 632
 633         if (init_done == 1 && dev < sata_info.maxport)
 634                 goto init_start;
 635
 636         init_done = 1;
 637
 638         /* Find PCI device(s) */
 639         devno = pci_find_devices(supported, idx++);
 640         if (devno == -1)
 641                 return 1;
 642
 643         pci_read_config_word(devno, PCI_DEVICE_ID, &word);
 644
 645         /* get the port count */
 646         word &= 0xf;
 647
 648         sata_info.portbase = 0;
 649         sata_info.maxport = sata_info.portbase + word;
 650         sata_info.devno = devno;
 651
 652         /* Read out all BARs */
 653         sata_info.iobase[0] = (ulong)pci_map_bar(devno,
 654                         PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 655         sata_info.iobase[1] = (ulong)pci_map_bar(devno,
 656                         PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
 657
 658         /* mask out the unused bits */
 659         sata_info.iobase[0] &= 0xffffff80;
 660         sata_info.iobase[1] &= 0xfffffc00;
 661
 662         /* Enable Bus Mastering and memory region */
 663         pci_write_config_word(devno, PCI_COMMAND,
 664                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 665
 666         /* Check if mem accesses and Bus Mastering are enabled. */
 667         pci_read_config_word(devno, PCI_COMMAND, &word);
 668         if (!(word & PCI_COMMAND_MEMORY) ||
 669             (!(word & PCI_COMMAND_MASTER))) {
 670                 printf("Error: Can not enable MEM access or Bus Mastering.\n");
 671                 debug("PCI command: %04x\n", word);
 672                 return 1;
 673         }
 674
 675         /* GPIO off */
 676         writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
 677         /* clear global reset & mask interrupts during initialization */
 678         writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
 679
 680 init_start:
 681         return sil_init_sata(dev);
 682 }
 683
 684 int reset_sata(int dev)
 685 {
 686         return 0;
 687 }
 688
 689 /*
 690  * SATA interface between low level driver and command layer
 691  */
 692 int scan_sata(int dev)
 693 {
 694         struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
 695 #else
 696 static int scan_sata(struct udevice *blk_dev, int dev)
 697 {
 698         struct blk_desc *desc = dev_get_uclass_platdata(blk_dev);
 699         struct sil_sata_priv *priv = dev_get_platdata(blk_dev);
 700         struct sil_sata *sata = priv->sil_sata_desc[dev];
 701 #endif
 702         unsigned char serial[ATA_ID_SERNO_LEN + 1];
 703         unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
 704         unsigned char product[ATA_ID_PROD_LEN + 1];
 705         u16 *id;
 706
 707         id = (u16 *)malloc(ATA_ID_WORDS * 2);
 708         if (!id) {
 709                 printf("Id malloc failed\n");
 710                 return 1;
 711         }
 712         sil_cmd_identify_device(sata, id);
 713
 714         sil_sata_set_feature_by_id(sata, id);
 715
 716         /* Serial number */
 717         ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
 718
 719         /* Firmware version */
 720         ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
 721
 722         /* Product model */
 723         ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 724
 725 #if !CONFIG_IS_ENABLED(BLK)
 726         memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
 727         memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
 728         memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
 729         /* Totoal sectors */
 730         sata_dev_desc[dev].lba = ata_id_n_sectors(id);
 731 #ifdef CONFIG_LBA48
 732         sata_dev_desc[dev].lba48 = sata->lba48;
 733 #endif
 734 #else
 735         memcpy(desc->product, serial, sizeof(serial));
 736         memcpy(desc->revision, firmware, sizeof(firmware));
 737         memcpy(desc->vendor, product, sizeof(product));
 738         desc->lba = ata_id_n_sectors(id);
 739 #ifdef CONFIG_LBA48
 740         desc->lba48 = sata->lba48;
 741 #endif
 742 #endif
 743
 744 #ifdef DEBUG
 745         ata_dump_id(id);
 746 #endif
 747         free((void *)id);
 748
 749         return 0;
 750 }
 751
 752 #if CONFIG_IS_ENABLED(BLK)
 753 static const struct blk_ops sata_sil_blk_ops = {
 754         .read   = sata_read,
 755         .write  = sata_write,
 756 };
 757
 758 U_BOOT_DRIVER(sata_sil_driver) = {
 759         .name = "sata_sil_blk",
 760         .id = UCLASS_BLK,
 761         .ops = &sata_sil_blk_ops,
 762         .platdata_auto_alloc_size = sizeof(struct sil_sata_priv),
 763 };
 764
 765 static int sil_pci_probe(struct udevice *dev)
 766 {
 767         struct udevice *blk;
 768         char sata_name[10];
 769         pci_dev_t devno;
 770         u16 word;
 771         int ret;
 772         int i;
 773
 774         /* Get PCI device number */
 775         devno = dm_pci_get_bdf(dev);
 776         if (devno == -1)
 777                 return 1;
 778
 779         dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
 780
 781         /* get the port count */
 782         word &= 0xf;
 783
 784         sata_info.portbase = 0;
 785         sata_info.maxport = sata_info.portbase + word;
 786         sata_info.devno = devno;
 787
 788         /* Read out all BARs */
 789         sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
 790                         PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 791         sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
 792                         PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
 793
 794         /* mask out the unused bits */
 795         sata_info.iobase[0] &= 0xffffff80;
 796         sata_info.iobase[1] &= 0xfffffc00;
 797
 798         /* Enable Bus Mastering and memory region */
 799         dm_pci_write_config16(dev, PCI_COMMAND,
 800                               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 801
 802         /* Check if mem accesses and Bus Mastering are enabled. */
 803         dm_pci_read_config16(dev, PCI_COMMAND, &word);
 804         if (!(word & PCI_COMMAND_MEMORY) ||
 805             (!(word & PCI_COMMAND_MASTER))) {
 806                 printf("Error: Can not enable MEM access or Bus Mastering.\n");
 807                 debug("PCI command: %04x\n", word);
 808                 return 1;
 809         }
 810
 811         /* GPIO off */
 812         writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
 813         /* clear global reset & mask interrupts during initialization */
 814         writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
 815
 816         for (i = sata_info.portbase; i < sata_info.maxport; i++) {
 817                 snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
 818                 ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
 819                                          IF_TYPE_SATA, -1, 512, 0, &blk);
 820                 if (ret) {
 821                         debug("Can't create device\n");
 822                         return ret;
 823                 }
 824
 825                 ret = sil_init_sata(blk, i);
 826                 if (ret)
 827                         return -ENODEV;
 828
 829                 ret = scan_sata(blk, i);
 830                 if (ret)
 831                         return -ENODEV;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int sata_sil_scan(struct udevice *dev)
 838 {
 839         /* Nothing to do here */
 840
 841         return 0;
 842 }
 843
 844 struct sil_ops sata_sil_ops = {
 845         .scan = sata_sil_scan,
 846 };
 847
 848 static const struct udevice_id sil_pci_ids[] = {
 849         { .compatible = "sil-pci-sample" },
 850         { }
 851 };
 852
 853 U_BOOT_DRIVER(sil_ahci_pci) = {
 854         .name   = "sil_ahci_pci",
 855         .id     = UCLASS_AHCI,
 856         .of_match = sil_pci_ids,
 857         .ops = &sata_sil_ops,
 858         .probe = sil_pci_probe,
 859         .priv_auto_alloc_size = sizeof(struct sil_sata_priv),
 860 };
 861
 862 U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
 863 #endif