2 * (C) Copyright 2017, Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
6 * Rockchip SARADC driver for U-Boot
16 #define SARADC_CTRL_CHN_MASK GENMASK(2, 0)
17 #define SARADC_CTRL_POWER_CTRL BIT(3)
18 #define SARADC_CTRL_IRQ_ENABLE BIT(5)
19 #define SARADC_CTRL_IRQ_STATUS BIT(6)
21 #define SARADC_TIMEOUT (100 * 1000)
23 struct rockchip_saradc_regs {
27 unsigned int dly_pu_soc;
30 struct rockchip_saradc_data {
33 unsigned long clk_rate;
36 struct rockchip_saradc_priv {
37 struct rockchip_saradc_regs *regs;
39 const struct rockchip_saradc_data *data;
42 int rockchip_saradc_channel_data(struct udevice *dev, int channel,
45 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
46 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
48 if (channel != priv->active_channel) {
49 pr_err("Requested channel is not active!");
53 if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) !=
54 SARADC_CTRL_IRQ_STATUS)
58 *data = readl(&priv->regs->data);
59 *data &= uc_pdata->data_mask;
62 writel(0, &priv->regs->ctrl);
67 int rockchip_saradc_start_channel(struct udevice *dev, int channel)
69 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
71 if (channel < 0 || channel >= priv->data->num_channels) {
72 pr_err("Requested channel is invalid!");
76 /* 8 clock periods as delay between power up and start cmd */
77 writel(8, &priv->regs->dly_pu_soc);
79 /* Select the channel to be used and trigger conversion */
80 writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) |
81 SARADC_CTRL_IRQ_ENABLE, &priv->regs->ctrl);
83 priv->active_channel = channel;
88 int rockchip_saradc_stop(struct udevice *dev)
90 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
93 writel(0, &priv->regs->ctrl);
95 priv->active_channel = -1;
100 int rockchip_saradc_probe(struct udevice *dev)
102 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
106 ret = clk_get_by_index(dev, 0, &clk);
110 ret = clk_set_rate(&clk, priv->data->clk_rate);
111 if (IS_ERR_VALUE(ret))
114 priv->active_channel = -1;
119 int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)
121 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
122 struct rockchip_saradc_priv *priv = dev_get_priv(dev);
123 struct rockchip_saradc_data *data;
125 data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
126 priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
127 if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
128 pr_err("Dev: %s - can't get address!", dev->name);
133 uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;;
134 uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
135 uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;
136 uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;
141 static const struct adc_ops rockchip_saradc_ops = {
142 .start_channel = rockchip_saradc_start_channel,
143 .channel_data = rockchip_saradc_channel_data,
144 .stop = rockchip_saradc_stop,
147 static const struct rockchip_saradc_data saradc_data = {
153 static const struct rockchip_saradc_data rk3066_tsadc_data = {
159 static const struct rockchip_saradc_data rk3399_saradc_data = {
165 static const struct udevice_id rockchip_saradc_ids[] = {
166 { .compatible = "rockchip,saradc",
167 .data = (ulong)&saradc_data },
168 { .compatible = "rockchip,rk3066-tsadc",
169 .data = (ulong)&rk3066_tsadc_data },
170 { .compatible = "rockchip,rk3399-saradc",
171 .data = (ulong)&rk3399_saradc_data },
175 U_BOOT_DRIVER(rockchip_saradc) = {
176 .name = "rockchip_saradc",
178 .of_match = rockchip_saradc_ids,
179 .ops = &rockchip_saradc_ops,
180 .probe = rockchip_saradc_probe,
181 .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata,
182 .priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv),