1 U-Boot for Freescale i.MX6
3 This file contains information for the port of U-Boot to the Freescale i.MX6
6 1. CONVENTIONS FOR FUSE ASSIGNMENTS
7 -----------------------------------
9 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
10 16 msbs in word 3[15:0].
11 For i.MX6SX and i.MX6UL, they have two MAC addresses. The second MAC address
12 is stored in fuse bank 4, with the 16 lsb in word 3[31:16] and the 32 msbs in
17 For reading the MAC address fuses on a MX6Q:
19 - The MAC address is stored in two fuse addresses (the fuse addresses are
20 described in the Fusemap Descriptions table from the mx6q Reference Manual):
22 0x620[31:0] - MAC_ADDR[31:0]
23 0x630[15:0] - MAC_ADDR[47:32]
25 In order to use the fuse API, we need to pass the bank and word values, which
26 are calculated as below:
28 Fuse address for the lower MAC address: 0x620
29 Base address for the fuses: 0x400
31 (0x620 - 0x400)/0x10 = 0x22 = 34 decimal
33 As the fuses are arranged in banks of 8 words:
35 34 / 8 = 4 and the remainder is 2, so in this case:
40 And the U-Boot command would be:
45 Word 0x00000002: 9f027772
47 Doing the same for the upper MAC address:
49 Fuse address for the upper MAC address: 0x630
50 Base address for the fuses: 0x400
52 (0x630 - 0x400)/0x10 = 0x23 = 35 decimal
54 As the fuses are arranged in banks of 8 words:
56 35 / 8 = 4 and the remainder is 3, so in this case:
61 And the U-Boot command would be:
66 Word 0x00000003: 00000004
68 ,which matches the ethaddr value:
72 Some other useful hints:
74 - The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference
75 Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register
76 Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual,
77 Rev. 1, 04/2013" document. For example, for the MAC fuses we have:
80 21B_C620 Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0)
82 21B_C630 Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1)
84 - The command '=> fuse read 4 2 2' reads the whole MAC addresses at once:
89 Word 0x00000002: 9f027772 00000004
91 NAND Boot on i.MX6 with SPL support
92 --------------------------------------
94 Writing/updating boot image in nand device is not straight forward in
95 i.MX6 platform and it requires boot control block(BCB) to be configured.
97 BCB contains two data structures, Firmware Configuration Block(FCB) and
98 Discovered Bad Block Table(DBBT). FCB has nand timings, DBBT search area,
99 and firmware. See IMX6DQRM Section 8.5.2.2
100 for more information.
102 We can't use 'nand write' command to write SPL/firmware image directly
103 like other platforms does. So we need special setup to write BCB block
104 as per IMX6QDL reference manual 'nandbcb update' command do that job.
106 for nand boot, up on reset bootrom look for FCB structure in
107 first block's if FCB found the nand timings are loaded for
108 further reads. once FCB read done, DTTB will be loaded and
109 finally firmware will be loaded which is boot image.
111 cmd_nandbcb will create FCB these structures
112 by taking mtd partition as an example.
113 - initial code will erase entire partition
114 - followed by FCB setup, like first 2 blocks for FCB/DBBT write,
115 and next block for FW1/SPL
116 - write firmware at FW1 block and
117 - finally write fcb/dttb in first 2 block.
119 Typical NAND BCB layout:
120 =======================
122 no.of blocks = partition size / erasesize
123 no.of fcb/dbbt blocks = 2
124 FW1 offset = no.of fcb/dbbt
127 -------------------------------
128 |FCB/DBBT 0|FCB/DBBT 1| FW 1 |
129 --------------------------------
131 On summary, nandbcb update will
132 - erase the entire partition
133 - create BCB by creating 2 FCB/BDDT block followed by
134 1 FW blocks based on partition size and erasesize.
135 - fill FCB/DBBT structures
136 - write FW/SPL in FW1
137 - write FCB/DBBT in first 2 blocks
141 icorem6qdl> ext4load mmc 0:1 $loadaddr SPL
142 39936 bytes read in 10 ms (3.8 MiB/s)
144 icorem6qdl> nandbcb update $loadaddr spl $filesize
145 device 0 offset 0x0, size 0x9c00
146 Erasing at 0x1c0000 -- 100% complete.
147 NAND fw write: 0x80000 offset, 0xb000 bytes written: OK
149 step-2: write u-boot-dtb.img
151 icorem6qdl> nand erase.part uboot
153 NAND erase.part: device 0 offset 0x200000, size 0x200000
154 Erasing at 0x3c0000 -- 100% complete.
157 icorem6qdl> ext4load mmc 0:1 $loadaddr u-boot-dtb.img
158 589094 bytes read in 37 ms (15.2 MiB/s)
160 icorem6qdl> nand write ${loadaddr} uboot ${filesize}
162 NAND write: device 0 offset 0x200000, size 0x8fd26
163 589094 bytes written: OK