1 The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
2 pins (mpp) to a specific function.
3 A Marvell SoC pin configuration node is a node of a group of pins which can
4 be used for a specific device or function. Each node requires one or more
5 mpp pins or group of pins and a mpp function common to all pins.
7 Required properties for the pinctrl driver:
8 - compatible: "marvell,mvebu-pinctrl",
9 "marvell,ap806-pinctrl",
10 "marvell,armada-7k-pinctrl",
11 "marvell,armada-8k-cpm-pinctrl",
12 "marvell,armada-8k-cps-pinctrl"
13 - bank-name: A string defining the pinc controller bank name
14 - reg: A pair of values defining the pin controller base address
16 - pin-count: Numeric value defining the amount of multi purpose pins
18 - max-func: Numeric value defining the maximum function value for
20 - pin-func: Array of pin function values for every pin in the bank.
21 When the function value for a specific pin equal 0xFF,
22 the pin configuration is skipped and a default function
23 value is used for this pin.
25 The A8K is a hybrid SoC that contains several silicon dies interconnected in
26 a single package. Each such die may have a separate pin controller.
32 pinctl: pinctl@6F4000 {
33 compatible = "marvell,mvebu-pinctrl",
34 "marvell,ap806-pinctrl";
36 reg = <0x6F4000 0x10>;
44 /* 0 1 2 3 4 5 6 7 8 9 */
45 pin-func = < 3 3 3 3 3 3 0 0 0 0
53 cpm_pinctl: pinctl@44000 {
54 compatible = "marvell,mvebu-pinctrl",
55 "marvell,armada-7k-pinctrl",
56 "marvell,armada-8k-cpm-pinctrl";
58 reg = <0x440000 0x20>;
62 * [0-31] = 0xff: Keep default CP0_shared_pins:
63 * [11] CLKOUT_MPP_11 (out)
64 * [23] LINK_RD_IN_CP2CP (in)
65 * [25] CLKOUT_MPP_25 (out)
66 * [29] AVS_FB_IN_CP2CP (in)
68 * [31] GPIO: push button/Wake
71 * [40-41] SATA[0/1]_PRESENT_ACTIVEn
76 /* 0 1 2 3 4 5 6 7 8 9 */
77 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
78 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
79 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
80 0xff 0 7 0 7 0 0 2 2 0
82 1 1 1 1 1 1 0xE 0xE 0xE 0xE
90 cps_pinctl: pinctl@44000 {
91 compatible = "marvell,mvebu-pinctrl",
92 "marvell,armada-8k-cps-pinctrl";
94 reg = <0x440000 0x20>;
100 * [32-62] = 0xff: Keep default CP1_shared_pins:
102 /* 0 1 2 3 4 5 6 7 8 9 */
103 pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
104 0x3 0x3 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
105 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
106 0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
107 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
108 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff