doc/device-tree-bindings/net/mdio-mux.txt

   1 The expected structure of an MDIO MUX device tree node is described here.  This
   2 is heavily based on current Linux specification.
   3 One notable difference to Linux is that mdio-parent-bus is currently required
   4 by U-Boot, not optional as is in Linux.  Current U-Boot MDIO MUX udevice class
   5 implementation does not have specific support for MDIOs with an integrated MUX,
   6 the property should be made optional if such support is added.
   7
   8 The MDIO buses downstream of the MUX should be described in the device tree as
   9 child nodes as indicated below.
  10
  11 Required properties:
  12 mdio-parent-bus = a phandle to the MDIO bus used to perform actual I/O.  This is
  13                   typically a real MDIO device, unless there are cascaded MUXes.
  14 #address-cells = <1>, each MDIO group is identified by one 32b value.
  15 #size-cells = <0>
  16
  17 Other properties:
  18 The properties described here are sufficient for MDIO MUX DM class code, but
  19 MUX drivers may define additional properties, either required or optional.
  20
  21 Required properties in child nodes:
  22 reg = value to be configured on the MUX to select the respective downstream
  23       MDIO.
  24
  25 Child nodes should normally contain PHY nodes, referenced by phandle from
  26 ethernet nodes of the eth interfaces using these PHYs.
  27
  28 Example structure, extracted from Linux bindings document:
  29
  30         /* The parent MDIO bus. */
  31         smi1: mdio@1180000001900 {
  32                 compatible = "cavium,octeon-3860-mdio";
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35                 reg = <0x11800 0x00001900 0x0 0x40>;
  36         };
  37         /*
  38          * An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
  39          * pair of GPIO lines.  Child busses 2 and 3 populated with 4
  40          * PHYs each.
  41          */
  42         mdio-mux {
  43                 compatible = "mdio-mux-gpio";
  44                 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
  45                 mdio-parent-bus = <&smi1>;
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 mdio@2 {
  49                         reg = <2>;
  50                         #address-cells = <1>;
  51                         #size-cells = <0>;
  52                         phy11: ethernet-phy@1 {
  53                                 reg = <1>;
  54                                 compatible = "marvell,88e1149r";
  55                                 marvell,reg-init = <3 0x10 0 0x5777>,
  56                                         <3 0x11 0 0x00aa>,
  57                                         <3 0x12 0 0x4105>,
  58                                         <3 0x13 0 0x0a60>;
  59                                 interrupt-parent = <&gpio>;
  60                                 interrupts = <10 8>; /* Pin 10, active low */
  61                         };
  62                         phy12: ethernet-phy@2 {
  63                                 reg = <2>;
  64                                 compatible = "marvell,88e1149r";
  65                                 marvell,reg-init = <3 0x10 0 0x5777>,
  66                                         <3 0x11 0 0x00aa>,
  67                                         <3 0x12 0 0x4105>,
  68                                         <3 0x13 0 0x0a60>;
  69                                 interrupt-parent = <&gpio>;
  70                                 interrupts = <10 8>; /* Pin 10, active low */
  71                         };
  72                         phy13: ethernet-phy@3 {
  73                                 reg = <3>;
  74                                 compatible = "marvell,88e1149r";
  75                                 marvell,reg-init = <3 0x10 0 0x5777>,
  76                                         <3 0x11 0 0x00aa>,
  77                                         <3 0x12 0 0x4105>,
  78                                         <3 0x13 0 0x0a60>;
  79                                 interrupt-parent = <&gpio>;
  80                                 interrupts = <10 8>; /* Pin 10, active low */
  81                         };
  82                         phy14: ethernet-phy@4 {
  83                                 reg = <4>;
  84                                 compatible = "marvell,88e1149r";
  85                                 marvell,reg-init = <3 0x10 0 0x5777>,
  86                                         <3 0x11 0 0x00aa>,
  87                                         <3 0x12 0 0x4105>,
  88                                         <3 0x13 0 0x0a60>;
  89                                 interrupt-parent = <&gpio>;
  90                                 interrupts = <10 8>; /* Pin 10, active low */
  91                         };
  92                 };
  93                 mdio@3 {
  94                         reg = <3>;
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         phy21: ethernet-phy@1 {
  98                                 reg = <1>;
  99                                 compatible = "marvell,88e1149r";
 100                                 marvell,reg-init = <3 0x10 0 0x5777>,
 101                                         <3 0x11 0 0x00aa>,
 102                                         <3 0x12 0 0x4105>,
 103                                         <3 0x13 0 0x0a60>;
 104                                 interrupt-parent = <&gpio>;
 105                                 interrupts = <12 8>; /* Pin 12, active low */
 106                         };
 107                         phy22: ethernet-phy@2 {
 108                                 reg = <2>;
 109                                 compatible = "marvell,88e1149r";
 110                                 marvell,reg-init = <3 0x10 0 0x5777>,
 111                                         <3 0x11 0 0x00aa>,
 112                                         <3 0x12 0 0x4105>,
 113                                         <3 0x13 0 0x0a60>;
 114                                 interrupt-parent = <&gpio>;
 115                                 interrupts = <12 8>; /* Pin 12, active low */
 116                         };
 117                         phy23: ethernet-phy@3 {
 118                                 reg = <3>;
 119                                 compatible = "marvell,88e1149r";
 120                                 marvell,reg-init = <3 0x10 0 0x5777>,
 121                                         <3 0x11 0 0x00aa>,
 122                                         <3 0x12 0 0x4105>,
 123                                         <3 0x13 0 0x0a60>;
 124                                 interrupt-parent = <&gpio>;
 125                                 interrupts = <12 8>; /* Pin 12, active low */
 126                         };
 127                         phy24: ethernet-phy@4 {
 128                                 reg = <4>;
 129                                 compatible = "marvell,88e1149r";
 130                                 marvell,reg-init = <3 0x10 0 0x5777>,
 131                                         <3 0x11 0 0x00aa>,
 132                                         <3 0x12 0 0x4105>,
 133                                         <3 0x13 0 0x0a60>;
 134                                 interrupt-parent = <&gpio>;
 135                                 interrupts = <12 8>; /* Pin 12, active low */
 136                         };
 137                 };
 138         };