doc/device-tree-bindings/clock/st,stm32mp1.txt

   1 STMicroelectronics STM32MP1 clock tree initialization
   2 =====================================================
   3
   4 The STM32MP1 clock tree initialization is based on device tree information
   5 for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes.
   6
   7 RCC IP = st,stm32mp1-rcc
   8 ========================
   9
  10 The RCC IP is both a reset and a clock controller but this documentation only
  11 describes the fields added for clock tree initialization which are not present
  12 in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
  13 file.
  14
  15 This parent node may optionally have additional children nodes which define
  16 specific init values for RCC elements.
  17
  18 The added properties for clock tree initialization are:
  19
  20 Required properties:
  21 - st,clksrc : The clock sources configuration array in a platform specific
  22               order.
  23
  24   For the STM32MP15x family there are 9 clock sources selector which are
  25   configured in the following order:
  26         MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
  27
  28   Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE>
  29   from dt-bindings/clock/stm32mp1-clksrc.h.
  30
  31   Example:
  32         st,clksrc = <
  33                 CLK_MPU_PLL1P
  34                 CLK_AXI_PLL2P
  35                 CLK_MCU_PLL3P
  36                 CLK_PLL12_HSE
  37                 CLK_PLL3_HSE
  38                 CLK_PLL4_HSE
  39                 CLK_RTC_LSE
  40                 CLK_MCO1_DISABLED
  41                 CLK_MCO2_DISABLED
  42         >;
  43
  44 - st,clkdiv : The clock main dividers value specified in an array
  45               in a platform specific order.
  46
  47   When used, it shall describe the whole clock dividers tree.
  48
  49   For the STM32MP15x family there are 11 dividers values expected.
  50   They shall be configured in the following order:
  51                 MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
  52
  53   The each divider value uses the DIV coding defined in RCC associated
  54   register RCC_xxxDIVR. In most the case, it is:
  55                 0x0: not divided
  56                 0x1: division by 2
  57                 0x2: division by 4
  58                 0x3: division by 8
  59                 ...
  60
  61   Note that for RTC MCO1 MCO2, the coding is different:
  62                 0x0: not divided
  63                 0x1: division by 2
  64                 0x2: division by 3
  65                 0x3: division by 4
  66                 ...
  67
  68   Example:
  69         st,clkdiv = <
  70                 1 /*MPU*/
  71                 0 /*AXI*/
  72                 0 /*MCU*/
  73                 1 /*APB1*/
  74                 1 /*APB2*/
  75                 1 /*APB3*/
  76                 1 /*APB4*/
  77                 2 /*APB5*/
  78                 23 /*RTC*/
  79                 0 /*MCO1*/
  80                 0 /*MCO2*/
  81         >;
  82
  83 Optional Properties:
  84 - children for a PLL configuration with "st,stm32mp1-pll" compatible
  85
  86   each PLL children nodes for PLL1 to PLL4 (see ref manual for details)
  87   are listed with associated reg 0 to 3.
  88   PLLx is off when the associated node is absent or deactivated.
  89
  90   Here are the available properties for each PLL node:
  91     - compatible: should be "st,stm32mp1-pll"
  92
  93     - reg: index of the pll instance
  94
  95     - cfg: The parameters for PLL configuration in the following order:
  96            DIVM DIVN DIVP DIVQ DIVR Output.
  97
  98         DIVx values are defined as in RCC spec:
  99                 0x0: bypass (division by 1)
 100                 0x1: division by 2
 101                 0x2: division by 3
 102                 0x3: division by 4
 103                 ...
 104
 105         Output contains a bitfield for each output value (1:ON/0:OFF)
 106                 BIT(0) => output P : DIVPEN
 107                 BIT(1) => output Q : DIVQEN
 108                 BIT(2) => output R : DIVREN
 109           NB: macro PQR(p,q,r) can be used to build this value
 110               with p,q,r = 0 or 1.
 111
 112     - frac : Fractional part of the multiplication factor
 113              (optional, PLL is in integer mode when absent).
 114
 115     - csg : Clock Spreading Generator (optional) with parameters in the
 116             following order: MOD_PER INC_STEP SSCG_MODE.
 117
 118         MOD_PER: Modulation Period Adjustment
 119         INC_STEP: Modulation Depth Adjustment
 120         SSCG_MODE: Spread spectrum clock generator mode, with associated
 121                    defined from stm32mp1-clksrc.h:
 122                         - SSCG_MODE_CENTER_SPREAD = 0
 123                         - SSCG_MODE_DOWN_SPREAD = 1
 124
 125     Example:
 126         st,pll@0 {
 127                 compatible = "st,stm32mp1-pll";
 128                 reg = <0>;
 129                 cfg = < 1 53 0 0 0 1 >;
 130                 frac = < 0x810 >;
 131         };
 132         st,pll@1 {
 133                 compatible = "st,stm32mp1-pll";
 134                 reg = <1>;
 135                 cfg = < 1 43 1 0 0 PQR(0,1,1) >;
 136                 csg = < 10 20 1 >;
 137         };
 138         st,pll@2 {
 139                 compatible = "st,stm32mp1-pll";
 140                 reg = <2>;
 141                 cfg = < 2 85 3 13 3 0 >;
 142                 csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
 143                 };
 144         st,pll@3 {
 145                 compatible = "st,stm32mp1-pll";
 146                 reg = <3>;
 147                 cfg = < 2 78 4 7 9 3 >;
 148         };
 149
 150 - st,pkcs : used to configure the peripherals kernel clock selection.
 151
 152   The property is a list of peripheral kernel clock source identifiers defined
 153   by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file
 154   dt-bindings/clock/stm32mp1-clksrc.h.
 155
 156   st,pkcs may not list all the kernel clocks and has no ordering requirements.
 157
 158   Example:
 159         st,pkcs = <
 160                 CLK_STGEN_HSE
 161                 CLK_CKPER_HSI
 162                 CLK_USBPHY_PLL2P
 163                 CLK_DSI_PLL2Q
 164                 CLK_I2C46_HSI
 165                 CLK_UART1_HSI
 166                 CLK_UART24_HSI
 167         >;
 168
 169 other clocks = fixed-clock
 170 ==========================
 171
 172 The clock tree is also based on 5 fixed-clock in clocks node
 173 used to define the state of associated ST32MP1 oscillators:
 174   - clk-lsi
 175   - clk-lse
 176   - clk-hsi
 177   - clk-hse
 178   - clk-csi
 179
 180 At boot the clock tree initialization will
 181   - enable oscillators present in device tree and not disabled
 182     (node with status="disabled"),
 183   - disable HSI oscillator if the node is absent (always activated by bootrom)
 184     and not disabled (node with status="disabled").
 185
 186 Optional properties :
 187
 188 a) for external oscillator: "clk-lse", "clk-hse"
 189
 190   4 optional fields are managed
 191   - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP)
 192   - "st,digbypass" configures the bypass mode as full-swing digital
 193     signal (DIGBYP)
 194   - "st,css" activates the clock security system (HSECSSON, LSECSSON)
 195   - "st,drive" (only for LSE) contains the value of the drive for the
 196      oscillator (see LSEDRV_ defined in the file
 197      dt-bindings/clock/stm32mp1-clksrc.h)
 198
 199   Example board file:
 200         / {
 201                 clocks {
 202                         clk_hse: clk-hse {
 203                                 #clock-cells = <0>;
 204                                 compatible = "fixed-clock";
 205                                 clock-frequency = <64000000>;
 206                                 st,bypass;
 207                         };
 208
 209                         clk_lse: clk-lse {
 210                                 #clock-cells = <0>;
 211                                 compatible = "fixed-clock";
 212                                 clock-frequency = <32768>;
 213                                 st,css;
 214                                 st,drive = <LSEDRV_LOWEST>;
 215                         };
 216         };
 217
 218 b) for internal oscillator: "clk-hsi"
 219
 220   Internally HSI clock is fixed to 64MHz for STM32MP157 SoC.
 221   In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC
 222   doc). So this clock frequency is used to compute the expected HSI_DIV
 223   for the clock tree initialization.
 224
 225   Example with HSIDIV = /1:
 226         / {
 227                 clocks {
 228                         clk_hsi: clk-hsi {
 229                                 #clock-cells = <0>;
 230                                 compatible = "fixed-clock";
 231                                 clock-frequency = <64000000>;
 232                         };
 233         };
 234
 235   Example with HSIDIV = /2
 236         / {
 237                 clocks {
 238                         clk_hsi: clk-hsi {
 239                                 #clock-cells = <0>;
 240                                 compatible = "fixed-clock";
 241                                 clock-frequency = <32000000>;
 242                         };
 243         };
 244
 245 Example of clock tree initialization
 246 ====================================
 247
 248 / {
 249         clocks {
 250                 u-boot,dm-pre-reloc;
 251                 clk_hse: clk-hse {
 252                         u-boot,dm-pre-reloc;
 253                         #clock-cells = <0>;
 254                         compatible = "fixed-clock";
 255                         clock-frequency = <24000000>;
 256                         st,digbypass;
 257                 };
 258
 259                 clk_hsi: clk-hsi {
 260                         u-boot,dm-pre-reloc;
 261                         #clock-cells = <0>;
 262                         compatible = "fixed-clock";
 263                         clock-frequency = <64000000>;
 264                 };
 265
 266                 clk_lse: clk-lse {
 267                         u-boot,dm-pre-reloc;
 268                         #clock-cells = <0>;
 269                         compatible = "fixed-clock";
 270                         clock-frequency = <32768>;
 271                 };
 272
 273                 clk_lsi: clk-lsi {
 274                         u-boot,dm-pre-reloc;
 275                         #clock-cells = <0>;
 276                         compatible = "fixed-clock";
 277                         clock-frequency = <32000>;
 278                 };
 279
 280                 clk_csi: clk-csi {
 281                         u-boot,dm-pre-reloc;
 282                         #clock-cells = <0>;
 283                         compatible = "fixed-clock";
 284                         clock-frequency = <4000000>;
 285                 };
 286         };
 287
 288         soc {
 289
 290                 rcc: rcc@50000000 {
 291                         u-boot,dm-pre-reloc;
 292                         compatible = "st,stm32mp1-rcc", "syscon";
 293                         reg = <0x50000000 0x1000>;
 294                         #address-cells = <1>;
 295                         #size-cells = <0>;
 296                         #clock-cells = <1>;
 297                         #reset-cells = <1>;
 298                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 299
 300                         st,clksrc = <
 301                                 CLK_MPU_PLL1P
 302                                 CLK_AXI_PLL2P
 303                                 CLK_MCU_PLL3P
 304                                 CLK_PLL12_HSE
 305                                 CLK_PLL3_HSE
 306                                 CLK_PLL4_HSE
 307                                 CLK_RTC_LSE
 308                                 CLK_MCO1_DISABLED
 309                                 CLK_MCO2_DISABLED
 310                         >;
 311
 312                         st,clkdiv = <
 313                                 1 /*MPU*/
 314                                 0 /*AXI*/
 315                                 0 /*MCU*/
 316                                 1 /*APB1*/
 317                                 1 /*APB2*/
 318                                 1 /*APB3*/
 319                                 1 /*APB4*/
 320                                 2 /*APB5*/
 321                                 23 /*RTC*/
 322                                 0 /*MCO1*/
 323                                 0 /*MCO2*/
 324                         >;
 325
 326                         st,pkcs = <
 327                                 CLK_CKPER_HSE
 328                                 CLK_FMC_ACLK
 329                                 CLK_QSPI_ACLK
 330                                 CLK_ETH_DISABLED
 331                                 CLK_SDMMC12_PLL4P
 332                                 CLK_DSI_DSIPLL
 333                                 CLK_STGEN_HSE
 334                                 CLK_USBPHY_HSE
 335                                 CLK_SPI2S1_PLL3Q
 336                                 CLK_SPI2S23_PLL3Q
 337                                 CLK_SPI45_HSI
 338                                 CLK_SPI6_HSI
 339                                 CLK_I2C46_HSI
 340                                 CLK_SDMMC3_PLL4P
 341                                 CLK_USBO_USBPHY
 342                                 CLK_ADC_CKPER
 343                                 CLK_CEC_LSE
 344                                 CLK_I2C12_HSI
 345                                 CLK_I2C35_HSI
 346                                 CLK_UART1_HSI
 347                                 CLK_UART24_HSI
 348                                 CLK_UART35_HSI
 349                                 CLK_UART6_HSI
 350                                 CLK_UART78_HSI
 351                                 CLK_SPDIF_PLL4P
 352                                 CLK_FDCAN_PLL4Q
 353                                 CLK_SAI1_PLL3Q
 354                                 CLK_SAI2_PLL3Q
 355                                 CLK_SAI3_PLL3Q
 356                                 CLK_SAI4_PLL3Q
 357                                 CLK_RNG1_LSI
 358                                 CLK_RNG2_LSI
 359                                 CLK_LPTIM1_PCLK1
 360                                 CLK_LPTIM23_PCLK3
 361                                 CLK_LPTIM45_LSE
 362                         >;
 363
 364                         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 365                         pll1: st,pll@0 {
 366                                 compatible = "st,stm32mp1-pll";
 367                                 reg = <0>;
 368                                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 369                                 frac = < 0x800 >;
 370                                 u-boot,dm-pre-reloc;
 371                         };
 372
 373                         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
 374                                                R = 533 (DDR) */
 375                         pll2: st,pll@1 {
 376                                 compatible = "st,stm32mp1-pll";
 377                                 reg = <1>;
 378                                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 379                                 frac = < 0x1400 >;
 380                                 u-boot,dm-pre-reloc;
 381                         };
 382
 383                         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 384                         pll3: st,pll@2 {
 385                                 compatible = "st,stm32mp1-pll";
 386                                 reg = <2>;
 387                                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 388                                 frac = < 0x1a04 >;
 389                                 u-boot,dm-pre-reloc;
 390                         };
 391
 392                         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 393                         pll4: st,pll@3 {
 394                                 compatible = "st,stm32mp1-pll";
 395                                 reg = <3>;
 396                                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 397                                 u-boot,dm-pre-reloc;
 398                         };
 399                 };
 400         };
 401 };