1 STMicroelectronics STM32H7 Reset and Clock Controller
2 =====================================================
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
7 Please also refer to reset.txt for common reset controller binding usage.
10 - compatible: Should be:
13 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
18 - #clock-cells : from common clock binding; shall be set to 1
20 - clocks: External oscillator clock phandle
21 - high speed external clock signal (HSE)
22 - low speed external clock signal (LSE)
23 - external I2S clock (I2S_CKIN)
25 - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
26 write protection (RTC clock).
28 - pll x node: Allow to register a pll with specific parameters.
29 Please see PLL section below.
36 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
37 reg = <0x58024400 0x400>;
38 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
40 st,syscfg = <&pwrcfg>;
47 compatible = "stm32,pll";
53 compatible = "stm32,pll";
68 The VCO of STM32 PLL could be reprensented like this:
70 Vref --------- --------
71 ---->| / DIVM |---->| x DIVN | ------> VCO
79 When the PLL is configured in integer mode:
80 - VCO = ( Vref / DIVM ) * DIVN
82 When the PLL is configured in fractional mode:
83 - VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)
86 Required properties for pll node:
87 - compatible: Should be:
90 - #clock-cells: from common clock binding; shall be set to 0
91 - reg: Should be the pll number.
94 - st,clock-div: DIVM division factor : <1..63>
95 - st,clock-mult: DIVN multiplication factor : <4..512>
98 - 0 Pll is configured in integer mode
99 - 1 Pll is configure in fractional mode
101 - st,frac: Fractional part of the multiplication factor : <0..8191>
103 - st,vcosel: VCO selection
104 - 0: Wide VCO range:192 to 836 MHz
105 - 1: Medium VCO range:150 to 420 MHz
107 - st,pllrge: PLL input frequency range
108 - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz
109 - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz
110 - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz
111 - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
114 The peripheral clock consumer should specify the desired clock by
115 having the clock ID in its "clocks" phandle cell.
117 All available clocks are defined as preprocessor macros in
118 dt-bindings/clock/stm32h7-clks.h header and can be used in device
123 timer5: timer@40000c00 {
124 compatible = "st,stm32-timer";
125 reg = <0x40000c00 0x400>;
127 clocks = <&rcc TIM5_CK>;
131 Specifying softreset control of devices
132 =======================================
134 Device nodes should specify the reset channel required in their "resets"
135 property, containing a phandle to the reset device node and an index specifying
136 which channel to use.
137 The index is the bit number within the RCC registers bank, starting from RCC
139 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
140 Where bit_offset is the bit offset within the register.
142 For example, for CRC reset:
143 crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
145 All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h
146 header and can be used in device tree sources.
151 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;