1 STMicroelectronics STM32 Reset and Clock Controller
2 ===================================================
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
7 Please also refer to reset.txt for common reset controller binding usage.
10 - compatible: Should be:
13 - reg: should be register base and length as documented in the
15 - #reset-cells: 1, see below
16 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
17 property, containing a phandle to the clock device node, an index selecting
18 between gated clocks and other clocks and an index specifying the clock to
26 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
27 reg = <0x40023800 0x400>;
30 Specifying gated clocks
31 =======================
33 The primary index must be set to 0.
35 The secondary index is the bit number within the RCC register bank, starting
36 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
38 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
39 Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
41 To simplify the usage and to share bit definition with the reset and clock
42 drivers of the RCC IP, macros are available to generate the index in
45 For STM32F4 series, the macro are available here:
46 - include/dt-bindings/mfd/stm32f4-rcc.h
50 /* Gated clock, AHB1 bit 0 (GPIOA) */
52 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
55 /* Gated clock, AHB2 bit 4 (CRYP) */
57 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
60 Specifying other clocks
61 =======================
63 The primary index must be set to 1.
65 The secondary index is bound with the following magic numbers:
72 /* Misc clock, FCLK */
74 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
78 Specifying softreset control of devices
79 =======================================
81 Device nodes should specify the reset channel required in their "resets"
82 property, containing a phandle to the reset device node and an index specifying
84 The index is the bit number within the RCC registers bank, starting from RCC
86 It is calculated as: index = register_offset / 4 * 32 + bit_offset.
87 Where bit_offset is the bit offset within the register.
88 For example, for CRC reset:
89 crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
94 resets = <&rcc STM32F4_APB1_RESET(TIM2)>;