1 .. SPDX-License-Identifier: GPL-2.0+
2 .. sectionauthor:: Simon Glass <sjg@chromium.org>
7 First, you need the following binary blobs:
9 * descriptor.bin - Intel flash descriptor
10 * me.bin - Intel Management Engine
11 * mrc.bin - Memory Reference Code, which sets up SDRAM
12 * refcode.elf - Additional Reference code
13 * vga.bin - video ROM, which sets up the display
15 If you have a samus you can obtain them from your flash, for example, in
16 developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
21 scp samus.bin username@ip_address:/path/to/somewhere
23 If not see the coreboot tree where you can use::
25 bash crosfirmware.sh samus
27 to get the image. There is also an 'extract_blobs.sh' scripts that you can use
28 on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
30 Then 'ifdtool -x samus.bin' on your development machine will produce::
32 flashregion_0_flashdescriptor.bin
33 flashregion_1_bios.bin
34 flashregion_2_intel_me.bin
36 Rename flashregion_0_flashdescriptor.bin to descriptor.bin
37 Rename flashregion_2_intel_me.bin to me.bin
38 You can ignore flashregion_1_bios.bin - it is not used.
40 To get the rest, use 'cbfstool samus.bin print'::
42 samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
43 alignment: 64 bytes, architecture: x86
45 ============================ ======== =========== ======
47 ============================ ======== =========== ======
48 cmos_layout.bin 0x700000 cmos_layout 1164
49 pci8086,0406.rom 0x7004c0 optionrom 65536
50 spd.bin 0x710500 (unknown) 4096
51 cpu_microcode_blob.bin 0x711540 microcode 70720
52 fallback/romstage 0x722a00 stage 54210
53 fallback/ramstage 0x72fe00 stage 96382
54 config 0x7476c0 raw 6075
55 fallback/vboot 0x748ec0 stage 15980
56 fallback/refcode 0x74cd80 stage 75578
57 fallback/payload 0x75f500 payload 62878
58 u-boot.dtb 0x76eb00 (unknown) 5318
59 (empty) 0x770000 null 196504
60 mrc.bin 0x79ffc0 (unknown) 222876
61 (empty) 0x7d66c0 null 167320
62 ============================ ======== =========== ======
64 You can extract what you need::
66 cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
67 cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
68 cbfstool samus.bin extract -n mrc.bin -f mrc.bin
69 cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
71 Note that the -U flag is only supported by the latest cbfstool. It unpacks
72 and decompresses the stage to produce a coreboot rmodule. This is a simple
73 representation of an ELF file. You need the patch "Support decoding a stage
76 Put all 5 files into board/google/chromebook_samus.
78 Now you can build U-Boot and obtain u-boot.rom::
80 $ make chromebook_samus_defconfig
83 If you are using em100, then this command will flash write -Boot::
85 em100 -s -d filename.rom -c W25Q64CV -r
87 Flash map for samus / broadwell:
89 :fffff800: SYS_X86_START16
90 :ffff0000: RESET_SEG_START
91 :fffd8000: TPL_TEXT_BASE
92 :fffa0000: X86_MRC_ADDR
93 :fff90000: VGA_BIOS_ADDR
94 :ffed0000: SYS_TEXT_BASE
95 :ffea0000: X86_REFCODE_ADDR
96 :ffe70000: SPL_TEXT_BASE
97 :ffbf8000: CONFIG_ENV_OFFSET (environemnt offset)
98 :ffbe0000: rw-mrc-cache (Memory-reference-code cache)
100 :ff801000: intel-me (address set by descriptor.bin)
101 :ff800000: intel-descriptor