2 # Copyright (C) 2014, Simon Glass <sjg@chromium.org>
3 # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
5 # SPDX-License-Identifier: GPL-2.0+
11 This document describes the information about U-Boot running on x86 targets,
12 including supported boards, build instructions, todo list, etc.
16 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17 (Chromebook Pixel) has been tested, but it should work with minimal adjustments
18 on other x86 boards since coreboot deals with most of the low-level details.
20 U-Boot also supports booting directly from x86 reset vector without coreboot,
21 aka raw support or bare support. Currently Link, Intel Crown Bay and Intel
22 Minnowboard Max support running U-Boot 'bare metal'.
24 As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
25 Linux kernel as part of a FIT image. It also supports a compressed zImage.
29 Building U-Boot as a coreboot payload is just like building U-Boot for targets
30 on other architectures, like below:
32 $ make coreboot-x86_defconfig
35 Note this default configuration will build a U-Boot payload for the Link board.
36 To build a coreboot payload against another board, you can change the build
37 configuration during the 'make menuconfig' process.
41 (chromebook_link) Board configuration file
42 (chromebook_link) Board Device Tree Source (dts) file
43 (0x19200000) Board specific Cache-As-RAM (CAR) address
44 (0x4000) Board specific Cache-As-RAM (CAR) size
46 Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
47 to point to a new board. You can also change the Cache-As-RAM (CAR) related
48 settings here if the default values do not fit your new board.
50 Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
51 little bit tricky, as generally it requires several binary blobs which are not
52 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
53 not turned on by default in the U-Boot source tree. Firstly, you need turn it
54 on by enabling the ROM build:
58 This tells the Makefile to build u-boot.rom as a target.
60 Link-specific instructions:
62 First, you need the following binary blobs:
64 * descriptor.bin - Intel flash descriptor
65 * me.bin - Intel Management Engine
66 * mrc.bin - Memory Reference Code, which sets up SDRAM
67 * video ROM - sets up the display
69 You can get these binary blobs by:
71 $ git clone http://review.coreboot.org/p/blobs.git
74 Find the following files:
76 * ./mainboard/google/link/descriptor.bin
77 * ./mainboard/google/link/me.bin
78 * ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
80 The 3rd one should be renamed to mrc.bin.
81 As for the video ROM, you can get it here [2].
82 Make sure all these binary blobs are put in the board directory.
84 Now you can build U-Boot and obtain u-boot.rom:
86 $ make chromebook_link_defconfig
89 Intel Crown Bay specific instructions:
91 U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
92 Firmware Support Package [4] to perform all the necessary initialization steps
93 as documented in the BIOS Writer Guide, including initialization of the CPU,
94 memory controller, chipset and certain bus interfaces.
96 Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
97 install it on your host and locate the FSP binary blob. Note this platform
98 also requires a Chipset Micro Code (CMC) state machine binary to be present in
99 the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
100 in this FSP package too.
102 * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
103 * ./Microcode/C0_22211.BIN
105 Rename the first one to fsp.bin and second one to cmc.bin and put them in the
108 Now you can build U-Boot and obtain u-boot.rom
110 $ make crownbay_defconfig
114 Intel Minnowboard Max instructions:
116 This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
117 Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
118 the time of writing). Put it in the board directory:
119 board/intel/minnowmax/fsp.bin
121 Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
122 directory: board/intel/minnowmax/vga.bin
124 You still need two more binary blobs. These come from the sample SPI image
125 provided in the FSP (SPI.bin at the time of writing).
127 Use ifdtool in the U-Boot tools directory to extract the images from that
130 $ ./tools/ifdtool -x BayleyBay/SPI.bin
131 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
132 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
134 Now you can build U-Boot and obtain u-boot.rom
136 $ make minnowmax_defconfig
142 For testing U-Boot as the coreboot payload, there are things that need be paid
143 attention to. coreboot supports loading an ELF executable and a 32-bit plain
144 binary, as well as other supported payloads. With the default configuration,
145 U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
146 generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
147 provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
148 this capability yet. The command is as follows:
150 # in the coreboot root directory
151 $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
152 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
154 Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
155 symbol address of _start (in arch/x86/cpu/start.S).
157 If you want to use ELF as the coreboot payload, change U-Boot configuration to
158 use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
160 To enable video you must enable these options in coreboot:
162 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
163 - Keep VESA framebuffer
165 At present it seems that for Minnowboard Max, coreboot does not pass through
166 the video information correctly (it always says the resolution is 0x0). This
167 works correctly for link though.
172 Modern CPUs usually require a special bit stream called microcode [5] to be
173 loaded on the processor after power up in order to function properly. U-Boot
174 has already integrated these as hex dumps in the source tree.
178 x86 has been converted to use driver model for serial and GPIO.
182 x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
183 be turned on. Not every device on the board is configured via device tree, but
184 more and more devices will be added as time goes by. Check out the directory
185 arch/x86/dts/ for these device tree source files.
190 In keeping with the U-Boot philosophy of providing functions to check and
191 adjust internal settings, there are several x86-specific commands that may be
194 hob - Display information about Firmware Support Package (FSP) Hand-off
195 Block. This is only available on platforms which use FSP, mostly
197 iod - Display I/O memory
198 iow - Write I/O memory
199 mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
200 tell the CPU whether memory is cacheable and if so the cache write
201 mode to use. U-Boot sets up some reasonable values but you can
202 adjust then with this command.
207 These notes are for those who want to port U-Boot to a new x86 platform.
209 Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
210 The Dediprog em100 can be used on Linux. The em100 tool is available here:
212 http://review.coreboot.org/p/em100.git
214 On Minnowboard Max the following command line can be used:
216 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
218 A suitable clip for connecting over the SPI flash chip is here:
220 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
222 This allows you to override the SPI flash contents for development purposes.
223 Typically you can write to the em100 in around 1200ms, considerably faster
224 than programming the real flash device each time. The only important
225 limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
226 This means that images must be set to boot with that speed. This is an
227 Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
228 speed in the SPI descriptor region.
230 If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
231 easy to fit it in. You can follow the Minnowboard Max implementation, for
232 example. Hopefully you will just need to create new files similar to those
233 in arch/x86/cpu/baytrail which provide Bay Trail support.
235 If you are not using an FSP you have more freedom and more responsibility.
236 The ivybridge support works this way, although it still uses a ROM for
237 graphics and still has binary blobs containing Intel code. You should aim to
238 support all important peripherals on your platform including video and storage.
239 Use the device tree for configuration where possible.
241 For the microcode you can create a suitable device tree file using the
244 ./tools/microcode-tool -d microcode.dat create <model>
246 or if you only have header files and not the full Intel microcode.dat database:
248 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
249 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
252 These are written to arch/x86/dts/microcode/ by default.
254 Note that it is possible to just add the micrcode for your CPU if you know its
255 model. U-Boot prints this information when it starts
257 CPU: x86_64, vendor Intel, device 30673h
259 so here we can use the M0130673322 file.
261 If you platform can display POST codes on two little 7-segment displays on
262 the board, then you can use post_code() calls from C or assembler to monitor
263 boot progress. This can be good for debugging.
265 If not, you can try to get serial working as early as possible. The early
266 debug serial port may be useful here. See setup_early_uart() for an example.
271 - Chrome OS verified boot
272 - SMI and ACPI support, to provide platform info and facilities to Linux
276 [1] http://www.coreboot.org
277 [2] http://www.coreboot.org/~stepan/pci8086,0166.rom
278 [3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
279 [4] http://www.intel.com/fsp
280 [5] http://en.wikipedia.org/wiki/Microcode