1 # SPDX-License-Identifier: GPL-2.0+
3 # Copyright (C) 2014, Simon Glass <sjg@chromium.org>
4 # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9 This document describes the information about U-Boot running on x86 targets,
10 including supported boards, build instructions, todo list, etc.
14 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
15 (Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should
16 work with minimal adjustments on other x86 boards since coreboot deals with
17 most of the low-level details.
19 U-Boot is a main bootloader on Intel Edison board.
21 U-Boot also supports booting directly from x86 reset vector, without coreboot.
22 In this case, known as bare mode, from the fact that it runs on the
23 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
28 - Congatec QEVAL 2.0 & conga-QA3/E3845
32 - Link (Chromebook Pixel)
34 - Samus (Chromebook Pixel 2015)
37 As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
38 Linux kernel as part of a FIT image. It also supports a compressed zImage.
39 U-Boot supports loading an x86 VxWorks kernel. Please check README.vxworks
42 Build Instructions for U-Boot as coreboot payload
43 -------------------------------------------------
44 Building U-Boot as a coreboot payload is just like building U-Boot for targets
45 on other architectures, like below:
47 $ make coreboot_defconfig
50 Build Instructions for U-Boot as main bootloader
51 ------------------------------------------------
53 Intel Edison instructions:
55 Simple you can build U-Boot and obtain u-boot.bin
57 $ make edison_defconfig
60 Build Instructions for U-Boot as BIOS replacement (bare mode)
61 -------------------------------------------------------------
62 Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
63 little bit tricky, as generally it requires several binary blobs which are not
64 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
65 not turned on by default in the U-Boot source tree. Firstly, you need turn it
66 on by enabling the ROM build either via an environment variable
74 Both tell the Makefile to build u-boot.rom as a target.
78 Chromebook Link specific instructions for bare mode:
80 First, you need the following binary blobs:
82 * descriptor.bin - Intel flash descriptor
83 * me.bin - Intel Management Engine
84 * mrc.bin - Memory Reference Code, which sets up SDRAM
85 * video ROM - sets up the display
87 You can get these binary blobs by:
89 $ git clone http://review.coreboot.org/p/blobs.git
92 Find the following files:
94 * ./mainboard/google/link/descriptor.bin
95 * ./mainboard/google/link/me.bin
96 * ./northbridge/intel/sandybridge/systemagent-r6.bin
98 The 3rd one should be renamed to mrc.bin.
99 As for the video ROM, you can get it here [3] and rename it to vga.bin.
100 Make sure all these binary blobs are put in the board directory.
102 Now you can build U-Boot and obtain u-boot.rom:
104 $ make chromebook_link_defconfig
109 Chromebook Samus (2015 Pixel) instructions for bare mode:
111 First, you need the following binary blobs:
113 * descriptor.bin - Intel flash descriptor
114 * me.bin - Intel Management Engine
115 * mrc.bin - Memory Reference Code, which sets up SDRAM
116 * refcode.elf - Additional Reference code
117 * vga.bin - video ROM, which sets up the display
119 If you have a samus you can obtain them from your flash, for example, in
120 developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
124 flashrom -w samus.bin
125 scp samus.bin username@ip_address:/path/to/somewhere
127 If not see the coreboot tree [4] where you can use:
129 bash crosfirmware.sh samus
131 to get the image. There is also an 'extract_blobs.sh' scripts that you can use
132 on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
134 Then 'ifdtool -x samus.bin' on your development machine will produce:
136 flashregion_0_flashdescriptor.bin
137 flashregion_1_bios.bin
138 flashregion_2_intel_me.bin
140 Rename flashregion_0_flashdescriptor.bin to descriptor.bin
141 Rename flashregion_2_intel_me.bin to me.bin
142 You can ignore flashregion_1_bios.bin - it is not used.
144 To get the rest, use 'cbfstool samus.bin print':
146 samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
147 alignment: 64 bytes, architecture: x86
149 Name Offset Type Size
150 cmos_layout.bin 0x700000 cmos_layout 1164
151 pci8086,0406.rom 0x7004c0 optionrom 65536
152 spd.bin 0x710500 (unknown) 4096
153 cpu_microcode_blob.bin 0x711540 microcode 70720
154 fallback/romstage 0x722a00 stage 54210
155 fallback/ramstage 0x72fe00 stage 96382
156 config 0x7476c0 raw 6075
157 fallback/vboot 0x748ec0 stage 15980
158 fallback/refcode 0x74cd80 stage 75578
159 fallback/payload 0x75f500 payload 62878
160 u-boot.dtb 0x76eb00 (unknown) 5318
161 (empty) 0x770000 null 196504
162 mrc.bin 0x79ffc0 (unknown) 222876
163 (empty) 0x7d66c0 null 167320
165 You can extract what you need:
167 cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
168 cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
169 cbfstool samus.bin extract -n mrc.bin -f mrc.bin
170 cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
172 Note that the -U flag is only supported by the latest cbfstool. It unpacks
173 and decompresses the stage to produce a coreboot rmodule. This is a simple
174 representation of an ELF file. You need the patch "Support decoding a stage
177 Put all 5 files into board/google/chromebook_samus.
179 Now you can build U-Boot and obtain u-boot.rom:
181 $ make chromebook_link_defconfig
184 If you are using em100, then this command will flash write -Boot:
186 em100 -s -d filename.rom -c W25Q64CV -r
190 Intel Crown Bay specific instructions for bare mode:
192 U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
193 Firmware Support Package [5] to perform all the necessary initialization steps
194 as documented in the BIOS Writer Guide, including initialization of the CPU,
195 memory controller, chipset and certain bus interfaces.
197 Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
198 install it on your host and locate the FSP binary blob. Note this platform
199 also requires a Chipset Micro Code (CMC) state machine binary to be present in
200 the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
201 in this FSP package too.
203 * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
204 * ./Microcode/C0_22211.BIN
206 Rename the first one to fsp.bin and second one to cmc.bin and put them in the
209 Note the FSP release version 001 has a bug which could cause random endless
210 loop during the FspInit call. This bug was published by Intel although Intel
211 did not describe any details. We need manually apply the patch to the FSP
212 binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
213 binary, change the following five bytes values from orginally E8 42 FF FF FF
216 As for the video ROM, you need manually extract it from the Intel provided
217 BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM
218 ID 8086:4108, extract and save it as vga.bin in the board directory.
220 Now you can build U-Boot and obtain u-boot.rom
222 $ make crownbay_defconfig
227 Intel Cougar Canyon 2 specific instructions for bare mode:
229 This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
230 with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
231 website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
232 time of writing) in the board directory and rename it to fsp.bin.
234 Now build U-Boot and obtain u-boot.rom
236 $ make cougarcanyon2_defconfig
239 The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
240 the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
241 and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
242 flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
243 this image to the SPI-0 flash according to the board manual just once and we are
244 all set. For programming U-Boot we just need to program SPI-1 flash. Since the
245 default u-boot.rom image for this board is set to 2MB, it should be programmed
246 to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
250 Intel Bay Trail based board instructions for bare mode:
252 This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
253 Two boards that use this configuration are Bayley Bay and Minnowboard MAX.
254 Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
255 the time of writing). Put it in the corresponding board directory and rename
258 Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
259 board directory as vga.bin.
261 You still need two more binary blobs. For Bayley Bay, they can be extracted
262 from the sample SPI image provided in the FSP (SPI.bin at the time of writing).
264 $ ./tools/ifdtool -x BayleyBay/SPI.bin
265 $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin
266 $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin
268 For Minnowboard MAX, we can reuse the same ME firmware above, but for flash
269 descriptor, we need get that somewhere else, as the one above does not seem to
270 work, probably because it is not designed for the Minnowboard MAX. Now download
271 the original firmware image for this board from:
273 http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
277 $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
279 Use ifdtool in the U-Boot tools directory to extract the images from that
282 $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
284 This will provide the descriptor file - copy this into the correct place:
286 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
288 Now you can build U-Boot and obtain u-boot.rom
289 Note: below are examples/information for Minnowboard MAX.
291 $ make minnowmax_defconfig
294 Checksums are as follows (but note that newer versions will invalidate this):
296 $ md5sum -b board/intel/minnowmax/*.bin
297 ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
298 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
299 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
300 a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
302 The ROM image is broken up into these parts:
304 Offset Description Controlling config
305 ------------------------------------------------------------
306 000000 descriptor.bin Hard-coded to 0 in ifdtool
307 001000 me.bin Set by the descriptor
309 6ef000 Environment CONFIG_ENV_OFFSET
310 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
311 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
312 7b0000 vga.bin CONFIG_VGA_BIOS_ADDR
313 7c0000 fsp.bin CONFIG_FSP_ADDR
314 7f8000 <spare> (depends on size of fsp.bin)
315 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
317 Overall ROM image size is controlled by CONFIG_ROM_SIZE.
319 Note that the debug version of the FSP is bigger in size. If this version
320 is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
321 the default value 0xfffc0000.
325 Intel Cherry Hill specific instructions for bare mode:
327 This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
328 put the .fd file to the board directory and rename it to fsp.bin.
330 Extract descriptor.bin and me.bin from the original BIOS on the board using
331 ifdtool and put them to the board directory as well.
333 Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
334 image for the integrated graphics device. Instead a new binary called Video
335 BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
336 vbt.bin if you want graphics support in U-Boot.
338 Now you can build U-Boot and obtain u-boot.rom
340 $ make cherryhill_defconfig
343 An important note for programming u-boot.rom to the on-board SPI flash is that
344 you need make sure the SPI flash's 'quad enable' bit in its status register
345 matches the settings in the descriptor.bin, otherwise the board won't boot.
347 For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
348 status register by DediProg in: Config > Modify Status Register > Write Status
349 Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
350 persists in SPI flash part regardless of the u-boot.rom image burned.
354 Intel Galileo instructions for bare mode:
356 Only one binary blob is needed for Remote Management Unit (RMU) within Intel
357 Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
358 needed by the Quark SoC itself.
360 You can get the binary blob from Quark Board Support Package from Intel website:
362 * ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
364 Rename the file and put it to the board directory by:
366 $ cp RMU.bin board/intel/galileo/rmu.bin
368 Now you can build U-Boot and obtain u-boot.rom
370 $ make galileo_defconfig
375 QEMU x86 target instructions for bare mode:
377 To build u-boot.rom for QEMU x86 targets, just simply run
379 $ make qemu-x86_defconfig
382 Note this default configuration will build a U-Boot for the QEMU x86 i440FX
383 board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
384 configuration during the 'make menuconfig' process like below:
386 Device Tree Control --->
388 (qemu-x86_q35) Default Device Tree for DT control
392 For testing U-Boot as the coreboot payload, there are things that need be paid
393 attention to. coreboot supports loading an ELF executable and a 32-bit plain
394 binary, as well as other supported payloads. With the default configuration,
395 U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
396 generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
397 provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
398 this capability yet. The command is as follows:
400 # in the coreboot root directory
401 $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
402 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
404 Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
405 of _x86boot_start (in arch/x86/cpu/start.S).
407 If you want to use ELF as the coreboot payload, change U-Boot configuration to
408 use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
410 To enable video you must enable these options in coreboot:
412 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
413 - Keep VESA framebuffer
415 And include coreboot_fb.dtsi in your board's device tree source file, like:
417 /include/ "coreboot_fb.dtsi"
419 At present it seems that for Minnowboard Max, coreboot does not pass through
420 the video information correctly (it always says the resolution is 0x0). This
421 works correctly for link though.
423 Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown
424 at this point. Patches are welcome if you figure out anything wrong.
426 Test with QEMU for bare mode
427 ----------------------------
428 QEMU is a fancy emulator that can enable us to test U-Boot without access to
429 a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
430 U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows:
432 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom
434 This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
435 also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
436 also supported by U-Boot. To instantiate such a machine, call QEMU with:
438 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
440 Note by default QEMU instantiated boards only have 128 MiB system memory. But
441 it is enough to have U-Boot boot and function correctly. You can increase the
442 system memory by pass '-m' parameter to QEMU if you want more memory:
444 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
446 This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
447 supports 3 GiB maximum system memory and reserves the last 1 GiB address space
448 for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
451 QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
452 show QEMU's VGA console window. Note this will disable QEMU's serial output.
453 If you want to check both consoles, use '-serial stdio'.
455 Multicore is also supported by QEMU via '-smp n' where n is the number of cores
456 to instantiate. Note, the maximum supported CPU number in QEMU is 255.
458 The fw_cfg interface in QEMU also provides information about kernel data,
459 initrd, command-line arguments and more. U-Boot supports directly accessing
460 these informtion from fw_cfg interface, which saves the time of loading them
461 from hard disk or network again, through emulated devices. To use it , simply
462 providing them in QEMU command line:
464 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
465 -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
467 Note: -initrd and -smp are both optional
469 Then start QEMU, in U-Boot command line use the following U-Boot command to
473 qfw - QEMU firmware interface
477 - list : print firmware(s) currently loaded
478 - cpus : print online cpu number
479 - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
482 loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
484 Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
485 'zboot' can be used to boot the kernel:
487 => zboot 01000000 - 04000000 1b1ab50
489 Updating U-Boot on Edison
490 -------------------------
491 By default Intel Edison boards are shipped with preinstalled heavily
492 patched U-Boot v2014.04. Though it supports DFU which we may be able to
495 1. Prepare u-boot.bin as described in chapter above. You still need one
496 more step (if and only if you have original U-Boot), i.e. run the
499 $ truncate -s %4096 u-boot.bin
501 2. Run your board and interrupt booting to U-Boot console. In the console
504 => run do_force_flash_os
506 3. Wait for few seconds, it will prepare environment variable and runs
507 DFU. Run DFU command from the host system:
509 $ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
511 4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
518 Modern CPUs usually require a special bit stream called microcode [8] to be
519 loaded on the processor after power up in order to function properly. U-Boot
520 has already integrated these as hex dumps in the source tree.
524 On a multicore system, U-Boot is executed on the bootstrap processor (BSP).
525 Additional application processors (AP) can be brought up by U-Boot. In order to
526 have an SMP kernel to discover all of the available processors, U-Boot needs to
527 prepare configuration tables which contain the multi-CPUs information before
528 loading the OS kernel. Currently U-Boot supports generating two types of tables
529 for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP)
530 [10] tables. The writing of these two tables are controlled by two Kconfig
531 options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
535 x86 has been converted to use driver model for serial, GPIO, SPI, SPI flash,
536 keyboard, real-time clock, USB. Video is in progress.
540 x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
541 be turned on. Not every device on the board is configured via device tree, but
542 more and more devices will be added as time goes by. Check out the directory
543 arch/x86/dts/ for these device tree source files.
547 In keeping with the U-Boot philosophy of providing functions to check and
548 adjust internal settings, there are several x86-specific commands that may be
551 fsp - Display information about Intel Firmware Support Package (FSP).
552 This is only available on platforms which use FSP, mostly Atom.
553 iod - Display I/O memory
554 iow - Write I/O memory
555 mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
556 tell the CPU whether memory is cacheable and if so the cache write
557 mode to use. U-Boot sets up some reasonable values but you can
558 adjust then with this command.
562 As an example of how to set up your boot flow with U-Boot, here are
563 instructions for starting Ubuntu from U-Boot. These instructions have been
564 tested on Minnowboard MAX with a SATA drive but are equally applicable on
565 other platforms and other media. There are really only four steps and it's a
566 very simple script, but a more detailed explanation is provided here for
569 Note: It is possible to set up U-Boot to boot automatically using syslinux.
570 It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
571 GUID. If you figure these out, please post patches to this README.
573 Firstly, you will need Ubuntu installed on an available disk. It should be
574 possible to make U-Boot start a USB start-up disk but for now let's assume
575 that you used another boot loader to install Ubuntu.
577 Use the U-Boot command line to find the UUID of the partition you want to
578 boot. For example our disk is SCSI device 0:
582 Partition Map for SCSI device 0 -- Partition Type: EFI
584 Part Start LBA End LBA Name
588 1 0x00000800 0x001007ff ""
589 attrs: 0x0000000000000000
590 type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
591 guid: 9d02e8e4-4d59-408f-a9b0-fd497bc9291c
592 2 0x00100800 0x037d8fff ""
593 attrs: 0x0000000000000000
594 type: 0fc63daf-8483-4772-8e79-3d69d8477de4
595 guid: 965c59ee-1822-4326-90d2-b02446050059
596 3 0x037d9000 0x03ba27ff ""
597 attrs: 0x0000000000000000
598 type: 0657fd6d-a4ab-43c4-84e5-0933c84b4f4f
599 guid: 2c4282bd-1e82-4bcf-a5ff-51dedbf39f17
602 This shows that your SCSI disk has three partitions. The really long hex
603 strings are called Globally Unique Identifiers (GUIDs). You can look up the
604 'type' ones here [11]. On this disk the first partition is for EFI and is in
605 VFAT format (DOS/Windows):
613 Partition 2 is 'Linux filesystem data' so that will be our root disk. It is
619 <DIR> 16384 lost+found
642 <SYM> 33 initrd.img.old
645 and if you look in the /boot directory you will see the kernel:
647 => ext2ls scsi 0:2 /boot
652 3381262 System.map-3.13.0-32-generic
653 1162712 abi-3.13.0-32-generic
654 165611 config-3.13.0-32-generic
655 176500 memtest86+.bin
656 178176 memtest86+.elf
657 178680 memtest86+_multiboot.bin
658 5798112 vmlinuz-3.13.0-32-generic
659 165762 config-3.13.0-58-generic
660 1165129 abi-3.13.0-58-generic
661 5823136 vmlinuz-3.13.0-58-generic
662 19215259 initrd.img-3.13.0-58-generic
663 3391763 System.map-3.13.0-58-generic
664 5825048 vmlinuz-3.13.0-58-generic.efi.signed
665 28304443 initrd.img-3.13.0-32-generic
668 The 'vmlinuz' files contain a packaged Linux kernel. The format is a kind of
669 self-extracting compressed file mixed with some 'setup' configuration data.
670 Despite its size (uncompressed it is >10MB) this only includes a basic set of
671 device drivers, enough to boot on most hardware types.
673 The 'initrd' files contain a RAM disk. This is something that can be loaded
674 into RAM and will appear to Linux like a disk. Ubuntu uses this to hold lots
675 of drivers for whatever hardware you might have. It is loaded before the
676 real root disk is accessed.
678 The numbers after the end of each file are the version. Here it is Linux
679 version 3.13. You can find the source code for this in the Linux tree with
680 the tag v3.13. The '.0' allows for additional Linux releases to fix problems,
681 but normally this is not needed. The '-58' is used by Ubuntu. Each time they
682 release a new kernel they increment this number. New Ubuntu versions might
683 include kernel patches to fix reported bugs. Stable kernels can exist for
684 some years so this number can get quite high.
686 The '.efi.signed' kernel is signed for EFI's secure boot. U-Boot has its own
687 secure boot mechanism - see [12] [13] and cannot read .efi files at present.
689 To boot Ubuntu from U-Boot the steps are as follows:
691 1. Set up the boot arguments. Use the GUID for the partition you want to
694 => setenv bootargs root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
696 Here root= tells Linux the location of its root disk. The disk is specified
697 by its GUID, using '/dev/disk/by-partuuid/', a Linux path to a 'directory'
698 containing all the GUIDs Linux has found. When it starts up, there will be a
699 file in that directory with this name in it. It is also possible to use a
700 device name here, see later.
702 2. Load the kernel. Since it is an ext2/4 filesystem we can do:
704 => ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic
706 The address 30000000 is arbitrary, but there seem to be problems with using
707 small addresses (sometimes Linux cannot find the ramdisk). This is 48MB into
708 the start of RAM (which is at 0 on x86).
710 3. Load the ramdisk (to 64MB):
712 => ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic
714 4. Start up the kernel. We need to know the size of the ramdisk, but can use
715 a variable for that. U-Boot sets 'filesize' to the size of the last file it
718 => zboot 03000000 0 04000000 ${filesize}
720 Type 'help zboot' if you want to see what the arguments are. U-Boot on x86 is
721 quite verbose when it boots a kernel. You should see these messages from
725 Setup Size = 0x00004400
726 Magic signature found
727 Using boot protocol version 2.0c
728 Linux kernel version 3.13.0-58-generic (buildd@allspice) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015
729 Building boot_params at 0x00090000
730 Loading bzImage at address 100000 (5805728 bytes)
731 Magic signature found
732 Initial RAM disk at linear address 0x04000000, size 19215259 bytes
733 Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
737 U-Boot prints out some bootstage timing. This is more useful if you put the
738 above commands into a script since then it will be faster.
740 Timer summary in microseconds:
743 241,535 241,535 board_init_r
744 2,421,611 2,180,076 id=64
746 2,428,215 6,425 main_loop
747 48,860,584 46,432,369 start_kernel
751 1,422,704 vesa display
753 Now the kernel actually starts: (if you want to examine kernel boot up message
754 on the serial console, append "console=ttyS0,115200" to the kernel command line)
756 [ 0.000000] Initializing cgroup subsys cpuset
757 [ 0.000000] Initializing cgroup subsys cpu
758 [ 0.000000] Initializing cgroup subsys cpuacct
759 [ 0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
760 [ 0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
762 It continues for a long time. Along the way you will see it pick up your
765 [ 0.000000] RAMDISK: [mem 0x04000000-0x05253fff]
767 [ 0.788540] Trying to unpack rootfs image as initramfs...
768 [ 1.540111] Freeing initrd memory: 18768K (ffff880004000000 - ffff880005254000)
771 Later it actually starts using it:
773 Begin: Running /scripts/local-premount ... done.
775 You should also see your boot disk turn up:
777 [ 4.357243] scsi 1:0:0:0: Direct-Access ATA ADATA SP310 5.2 PQ: 0 ANSI: 5
778 [ 4.366860] sd 1:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
779 [ 4.375677] sd 1:0:0:0: Attached scsi generic sg0 type 0
780 [ 4.381859] sd 1:0:0:0: [sda] Write Protect is off
781 [ 4.387452] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
782 [ 4.399535] sda: sda1 sda2 sda3
784 Linux has found the three partitions (sda1-3). Mercifully it doesn't print out
785 the GUIDs. In step 1 above we could have used:
787 setenv bootargs root=/dev/sda2 ro
789 instead of the GUID. However if you add another drive to your board the
790 numbering may change whereas the GUIDs will not. So if your boot partition
791 becomes sdb2, it will still boot. For embedded systems where you just want to
792 boot the first disk, you have that option.
794 The last thing you will see on the console is mention of plymouth (which
795 displays the Ubuntu start-up screen) and a lot of 'Starting' messages:
797 * Starting Mount filesystems on boot [ OK ]
799 After a pause you should see a login screen on your display and you are done.
801 If you want to put this in a script you can use something like this:
803 setenv bootargs root=UUID=b2aaf743-0418-4d90-94cc-3e6108d7d968 ro
804 setenv boot zboot 03000000 0 04000000 \${filesize}
805 setenv bootcmd "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; run boot"
808 The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
811 You can also bake this behaviour into your build by hard-coding the
812 environment variables if you add this to minnowmax.h:
814 #undef CONFIG_BOOTCOMMAND
815 #define CONFIG_BOOTCOMMAND \
816 "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; " \
817 "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \
820 #undef CONFIG_EXTRA_ENV_SETTINGS
821 #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
823 and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to:
825 CONFIG_BOOTARGS="root=/dev/sda2 ro"
829 SeaBIOS [14] is an open source implementation of a 16-bit x86 BIOS. It can run
830 in an emulator or natively on x86 hardware with the use of U-Boot. With its
831 help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS.
833 As U-Boot, we have to manually create a table where SeaBIOS gets various system
834 information (eg: E820) from. The table unfortunately has to follow the coreboot
835 table format as SeaBIOS currently supports booting as a coreboot payload.
837 To support loading SeaBIOS, U-Boot should be built with CONFIG_SEABIOS on.
838 Booting SeaBIOS is done via U-Boot's bootelf command, like below:
840 => tftp bios.bin.elf;bootelf
842 TFTP from server 10.10.0.100; our IP address is 10.10.0.108
844 Bytes transferred = 122124 (1dd0c hex)
845 ## Starting application at 0x000ff06e ...
846 SeaBIOS (version rel-1.9.0)
849 bios.bin.elf is the SeaBIOS image built from SeaBIOS source tree.
850 Make sure it is built as follows:
854 Inside the "General Features" menu, select "Build for coreboot" as the
855 "Build Target". Inside the "Debugging" menu, turn on "Serial port debugging"
856 so that we can see something as soon as SeaBIOS boots. Leave other options
857 as in their default state. Then,
861 Total size: 121888 Fixed: 66496 Free: 9184 (used 93.0% of 128KiB rom)
862 Creating out/bios.bin.elf
864 Currently this is tested on QEMU x86 target with U-Boot chain-loading SeaBIOS
865 to install/boot a Windows XP OS (below for example command to install Windows).
867 # Create a 10G disk.img as the virtual hard disk
868 $ qemu-img create -f qcow2 disk.img 10G
870 # Install a Windows XP OS from an ISO image 'winxp.iso'
871 $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -cdrom winxp.iso -smp 2 -m 512
873 # Boot a Windows XP OS installed on the virutal hard disk
874 $ qemu-system-i386 -serial stdio -bios u-boot.rom -hda disk.img -smp 2 -m 512
876 This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
877 SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
879 If you are using Intel Integrated Graphics Device (IGD) as the primary display
880 device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
881 loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
882 register, but IGD device does not have its VGA ROM mapped by this register.
883 Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
884 which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
886 diff --git a/src/optionroms.c b/src/optionroms.c
887 index 65f7fe0..c7b6f5e 100644
888 --- a/src/optionroms.c
889 +++ b/src/optionroms.c
890 @@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
891 rom = deploy_romfile(file);
892 else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
893 rom = map_pcirom(pci);
894 + if (pci->bdf == pci_to_bdf(0, 2, 0))
895 + rom = (struct rom_header *)0xfff90000;
900 Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
901 is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
902 Change these two accordingly if this is not the case on your board.
906 These notes are for those who want to port U-Boot to a new x86 platform.
908 Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
909 The Dediprog em100 can be used on Linux. The em100 tool is available here:
911 http://review.coreboot.org/p/em100.git
913 On Minnowboard Max the following command line can be used:
915 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
917 A suitable clip for connecting over the SPI flash chip is here:
919 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
921 This allows you to override the SPI flash contents for development purposes.
922 Typically you can write to the em100 in around 1200ms, considerably faster
923 than programming the real flash device each time. The only important
924 limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
925 This means that images must be set to boot with that speed. This is an
926 Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
927 speed in the SPI descriptor region.
929 If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
930 easy to fit it in. You can follow the Minnowboard Max implementation, for
931 example. Hopefully you will just need to create new files similar to those
932 in arch/x86/cpu/baytrail which provide Bay Trail support.
934 If you are not using an FSP you have more freedom and more responsibility.
935 The ivybridge support works this way, although it still uses a ROM for
936 graphics and still has binary blobs containing Intel code. You should aim to
937 support all important peripherals on your platform including video and storage.
938 Use the device tree for configuration where possible.
940 For the microcode you can create a suitable device tree file using the
943 ./tools/microcode-tool -d microcode.dat -m <model> create
945 or if you only have header files and not the full Intel microcode.dat database:
947 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
948 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
951 These are written to arch/x86/dts/microcode/ by default.
953 Note that it is possible to just add the micrcode for your CPU if you know its
954 model. U-Boot prints this information when it starts
956 CPU: x86_64, vendor Intel, device 30673h
958 so here we can use the M0130673322 file.
960 If you platform can display POST codes on two little 7-segment displays on
961 the board, then you can use post_code() calls from C or assembler to monitor
962 boot progress. This can be good for debugging.
964 If not, you can try to get serial working as early as possible. The early
965 debug serial port may be useful here. See setup_internal_uart() for an example.
967 During the U-Boot porting, one of the important steps is to write correct PIRQ
968 routing information in the board device tree. Without it, device drivers in the
969 Linux kernel won't function correctly due to interrupt is not working. Please
970 refer to U-Boot doc [15] for the device tree bindings of Intel interrupt router.
971 Here we have more details on the intel,pirq-routing property below.
973 intel,pirq-routing = <
974 PCI_BDF(0, 2, 0) INTA PIRQA
978 As you see each entry has 3 cells. For the first one, we need describe all pci
979 devices mounted on the board. For SoC devices, normally there is a chapter on
980 the chipset datasheet which lists all the available PCI devices. For example on
981 Bay Trail, this is chapter 4.3 (PCI configuration space). For the second one, we
982 can get the interrupt pin either from datasheet or hardware via U-Boot shell.
983 The reliable source is the hardware as sometimes chipset datasheet is not 100%
984 up-to-date. Type 'pci header' plus the device's pci bus/device/function number
985 from U-Boot shell below.
991 interrupt line = 0x09
995 It shows this PCI device is using INTD pin as it reports 4 in the interrupt pin
996 register. Repeat this until you get interrupt pins for all the devices. The last
997 cell is the PIRQ line which a particular interrupt pin is mapped to. On Intel
998 chipset, the power-up default mapping is INTA/B/C/D maps to PIRQA/B/C/D. This
999 can be changed by registers in LPC bridge. So far Intel FSP does not touch those
1000 registers so we can write down the PIRQ according to the default mapping rule.
1002 Once we get the PIRQ routing information in the device tree, the interrupt
1003 allocation and assignment will be done by U-Boot automatically. Now you can
1004 enable CONFIG_GENERATE_PIRQ_TABLE for testing Linux kernel using i8259 PIC and
1005 CONFIG_GENERATE_MP_TABLE for testing Linux kernel using local APIC and I/O APIC.
1007 This script might be useful. If you feed it the output of 'pci long' from
1008 U-Boot then it will generate a device tree fragment with the interrupt
1009 configuration for each device (note it needs gawk 4.0.0):
1011 $ cat console_output |awk '/PCI/ {device=$4} /interrupt line/ {line=$4} \
1012 /interrupt pin/ {pin = $4; if (pin != "0x00" && pin != "0xff") \
1013 {patsplit(device, bdf, "[0-9a-f]+"); \
1014 printf "PCI_BDF(%d, %d, %d) INT%c PIRQ%c\n", strtonum("0x" bdf[1]), \
1015 strtonum("0x" bdf[2]), bdf[3], strtonum(pin) + 64, 64 + strtonum(pin)}}'
1018 PCI_BDF(0, 2, 0) INTA PIRQA
1019 PCI_BDF(0, 3, 0) INTA PIRQA
1025 Quark-specific considerations:
1027 To port U-Boot to other boards based on the Intel Quark SoC, a few things need
1028 to be taken care of. The first important part is the Memory Reference Code (MRC)
1029 parameters. Quark MRC supports memory-down configuration only. All these MRC
1030 parameters are supplied via the board device tree. To get started, first copy
1031 the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
1032 change these values by consulting board manuals or your hardware vendor.
1033 Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
1034 The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
1035 but by default they are held in reset after power on. In U-Boot, PCIe
1036 initialization is properly handled as per Quark's firmware writer guide.
1037 In your board support codes, you need provide two routines to aid PCIe
1038 initialization, which are board_assert_perst() and board_deassert_perst().
1039 The two routines need implement a board-specific mechanism to assert/deassert
1040 PCIe PERST# pin. Care must be taken that in those routines that any APIs that
1041 may trigger PCI enumeration process are strictly forbidden, as any access to
1042 PCIe root port's configuration registers will cause system hang while it is
1043 held in reset. For more details, check how they are implemented by the Intel
1044 Galileo board support codes in board/intel/galileo/galileo.c.
1048 See scripts/coreboot.sed which can assist with porting coreboot code into
1049 U-Boot drivers. It will not resolve all build errors, but will perform common
1050 transformations. Remember to add attribution to coreboot for new files added
1051 to U-Boot. This should go at the top of each file and list the coreboot
1052 filename where the code originated.
1054 Debugging ACPI issues with Windows:
1056 Windows might cache system information and only detect ACPI changes if you
1057 modify the ACPI table versions. So tweak them liberally when debugging ACPI
1058 issues with Windows.
1062 Advanced Configuration and Power Interface (ACPI) [16] aims to establish
1063 industry-standard interfaces enabling OS-directed configuration, power
1064 management, and thermal management of mobile, desktop, and server platforms.
1066 Linux can boot without ACPI with "acpi=off" command line parameter, but
1067 with ACPI the kernel gains the capabilities to handle power management.
1068 For Windows, ACPI is a must-have firmware feature since Windows Vista.
1069 CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
1070 U-Boot. This requires Intel ACPI compiler to be installed on your host to
1071 compile ACPI DSDT table written in ASL format to AML format. You can get
1072 the compiler via "apt-get install iasl" if you are on Ubuntu or download
1073 the source from [17] to compile one by yourself.
1075 Current ACPI support in U-Boot is basically complete. More optional features
1076 can be added in the future. The status as of today is:
1078 * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
1079 * Support one static DSDT table only, compiled by Intel ACPI compiler.
1080 * Support S0/S3/S4/S5, reboot and shutdown from OS.
1081 * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
1082 * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
1083 the help of SeaBIOS using legacy interface (non-UEFI mode).
1084 * Support installing and booting Windows 8.1/10 from U-Boot with the help
1085 of SeaBIOS using legacy interface (non-UEFI mode).
1086 * Support ACPI interrupts with SCI only.
1088 Features that are optional:
1089 * Dynamic AML bytecodes insertion at run-time. We may need this to support
1090 SSDT table generation and DSDT fix up.
1091 * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
1092 those legacy stuff into U-Boot. ACPI spec allows a system that does not
1093 support SMI (a legacy-free system).
1095 ACPI was initially enabled on BayTrail based boards. Testing was done by booting
1096 a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
1097 Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
1098 devices seem to work correctly and the board can respond a reboot/shutdown
1099 command from the OS.
1101 For other platform boards, ACPI support status can be checked by examining their
1102 board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
1104 The S3 sleeping state is a low wake latency sleeping state defined by ACPI
1105 spec where all system context is lost except system memory. To test S3 resume
1106 with a Linux kernel, simply run "echo mem > /sys/power/state" and kernel will
1107 put the board to S3 state where the power is off. So when the power button is
1108 pressed again, U-Boot runs as it does in cold boot and detects the sleeping
1109 state via ACPI register to see if it is S3, if yes it means we are waking up.
1110 U-Boot is responsible for restoring the machine state as it is before sleep.
1111 When everything is done, U-Boot finds out the wakeup vector provided by OSes
1112 and jump there. To determine whether ACPI S3 resume is supported, check to
1113 see if CONFIG_HAVE_ACPI_RESUME is set for that specific board.
1115 Note for testing S3 resume with Windows, correct graphics driver must be
1116 installed for your platform, otherwise you won't find "Sleep" option in
1117 the "Power" submenu from the Windows start menu.
1121 U-Boot supports booting as a 32-bit or 64-bit EFI payload, e.g. with UEFI.
1122 This is enabled with CONFIG_EFI_STUB to boot from both 32-bit and 64-bit
1123 UEFI BIOS. U-Boot can also run as an EFI application, with CONFIG_EFI_APP.
1124 The CONFIG_EFI_LOADER option, where U-Boot provides an EFI environment to
1125 the kernel (i.e. replaces UEFI completely but provides the same EFI run-time
1126 services) is supported too. For example, we can even use 'bootefi' command
1127 to load a 'u-boot-payload.efi', see below test logs on QEMU.
1129 => load ide 0 3000000 u-boot-payload.efi
1130 489787 bytes read in 138 ms (3.4 MiB/s)
1132 Scanning disk ide.blk#0...
1134 WARNING: booting without device tree
1135 ## Starting EFI application at 03000000 ...
1139 U-Boot 2018.07-rc2 (Jun 23 2018 - 17:12:58 +0800)
1141 CPU: x86_64, vendor AMD, device 663h
1145 Model: EFI x86 Payload
1146 Net: e1000: 52:54:00:12:34:56
1148 Warning: e1000#0 using MAC address from ROM
1150 No controllers found
1151 Hit any key to stop autoboot: 0
1153 See README.u-boot_on_efi and README.uefi for details of EFI support in U-Boot.
1157 U-Boot supports booting a 64-bit kernel directly and is able to change to
1158 64-bit mode to do so. However, U-Boot itself is currently always built
1159 in 32-bit mode. Some access to the full memory range is provided with
1162 The development work to make U-Boot itself run in 64-bit mode has not yet
1163 been attempted. The best approach would likely be to build a 32-bit SPL
1164 image for U-Boot, with CONFIG_SPL_BUILD. This could then handle the early CPU
1165 init in 16-bit and 32-bit mode, running the FSP and any other binaries that
1166 are needed. Then it could change to 64-bit model and jump to U-Boot proper.
1168 Given U-Boot's extensive 64-bit support this has not been a high priority,
1169 but it would be a nice addition.
1174 - Chrome OS verified boot
1175 - Building U-Boot to run in 64-bit mode
1179 [1] http://www.coreboot.org
1180 [2] http://www.qemu.org
1181 [3] http://www.coreboot.org/~stepan/pci8086,0166.rom
1182 [4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
1183 [5] http://www.intel.com/fsp
1184 [6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
1185 [7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
1186 [8] http://en.wikipedia.org/wiki/Microcode
1187 [9] http://simplefirmware.org
1188 [10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm
1189 [11] https://en.wikipedia.org/wiki/GUID_Partition_Table
1190 [12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
1191 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
1192 [14] http://www.seabios.org/SeaBIOS
1193 [15] doc/device-tree-bindings/misc/intel,irq-router.txt
1194 [16] http://www.acpi.info
1195 [17] https://www.acpica.org/downloads