4 The SBC8548 is a stand alone single board computer with a 1GHz
5 MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
7 and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
13 The following possible u-boot configuration targets are available:
16 2) sbc8548_PCI_33_config
17 3) sbc8548_PCI_66_config
18 4) sbc8548_PCI_33_PCIE_config
19 5) sbc8548_PCI_66_PCIE_config
21 Generally speaking, most people should choose to use #5. Details
22 of each choice are listed below.
24 Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
25 will be left empty (M66EN high), and so the board will operate with
26 a base clock of 66MHz. Note that you need both PCI enabled in u-boot
27 and linux in order to have functional PCI under linux.
29 The second enables PCI support and builds for a 33MHz clock rate. Note
30 that if a 33MHz 32bit card is inserted in the slot, then the whole board
31 will clock down to a 33MHz base clock instead of the default 66MHz. This
32 will change the baud clocks and mess up your serial console output if you
33 were previously running at 66MHz. If you want to use a 33MHz PCI card,
34 then you should build a U-Boot with a _PCI_33_ config and store this
35 to flash prior to powering down the board and inserting the 33MHz PCI
36 card. [The above discussion assumes that the SW2[1-4] has not been changed
37 to reflect a different CCB:SYSCLK ratio]
39 The third option builds PCI support in, and leaves the clocking at the
40 default 66MHz. Options four and five are just repeats of option two
41 and three, but with PCI-e support enabled as well.
43 PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
44 is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
45 a 33MHz PCI configuration is currently untested.)
48 Scanning PCI devices on bus 0
49 BusDevFun VendorId DeviceId Device Class Sub-Class
50 _____________________________________________________________
51 00.00.00 0x1057 0x0012 Processor 0x20
52 00.01.00 0x8086 0x1026 Network controller 0x00
54 Scanning PCI devices on bus 1
55 BusDevFun VendorId DeviceId Device Class Sub-Class
56 _____________________________________________________________
57 01.00.00 0x1957 0x0012 Processor 0x20
59 Scanning PCI devices on bus 2
60 BusDevFun VendorId DeviceId Device Class Sub-Class
61 _____________________________________________________________
62 02.00.00 0x1148 0x9e00 Network controller 0x00
69 The following contains some summary information on hardware settings
70 that are relevant to u-boot, based on the board manual. For the
71 most up to date and complete details of the board, please request the
72 reference manual ERG-00327-001.pdf from www.windriver.com
75 intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
78 intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
84 ----------------------------------------------------------------
85 JP12 CS0/CS6 swap see note[*] see note[*]
87 JP13 SODIMM flash write OK writes disabled
90 JP14 HRESET/TRST joined isolated
92 JP15 PWR ON when AC pwr use S1 for on/off
94 JP16 Demo LEDs lit not lit
96 JP19 PCI mode PCI PCI-X
99 [*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
100 onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
101 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
102 SODIMM flash and /CS6 is for the boot flash. Note that in this
103 alternate setting, you also need to switch SW2.8 to ON. Currently
104 u-boot doesn't support booting off the SODIMM in this alternate
105 setting without manually altering BR0/OR0 and BR6/OR6 in the
106 board config file appropriately.
111 The defaults are marked with a *
114 ------------------------------------------------------------------
115 S1 Pwr toggle n/a n/a
117 SW2.1 CFG_SYS_PLL0 1 0*
118 SW2.2 CFG_SYS_PLL1 1* 0
119 SW2.3 CFG_SYS_PLL2 1* 0
120 SW2.4 CFG_SYS_PLL3 1 0*
121 SW2.5 CFG_CORE_PLL0 1* 0
122 SW2.6 CFG_CORE_PLL1 1 0*
123 SW2.7 CFG_CORE_PLL2 1* 0
124 SW2.8 CFG_ROM_LOC1 1 0*
126 SW3.1 CFG_HOST_AGT0 1* 0
127 SW3.2 CFG_HOST_AGT1 1* 0
128 SW3.3 CFG_HOST_AGT2 1* 0
129 SW3.4 CFG_IO_PORTS0 1* 0
130 SW3.5 CFG_IO_PORTS0 1 0*
131 SW3.6 CFG_IO_PORTS0 1 0*
133 SerDes CLK(MHz) SW5.1 SW5.2
134 ----------------------------------------------
140 SerDes CLK spread SW5.3 SW5.4
141 ----------------------------------------------
147 SW4 settings are readable from the EPLD and are currently not used for
148 any hardware settings (i.e. user configuration switches).
153 ------------------------------------------------------------------
154 D13 PCI/PCI-X PCI-X PCI
155 D14 3.3V PWR 3.3V no power
156 D15 SYSCLK 66MHz 33MHz
161 start end CS<n> width Desc.
162 ----------------------------------------------------------------------
163 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
164 f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
165 f800_0000 f8b0_1fff CS5 - EPLD
166 fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB)
167 ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
169 The EPLD on CS5 demuxes the following devices at the following offsets:
171 offset size width device
172 --------------------------------------------------------
173 0 1fff 8 7 segment display LED
174 10_0000 1fff 4 user switches
175 30_0000 1fff 4 HW Rev. register
176 b0_0000 1fff 8 8kB EEPROM