1 Freescale MPC8641HPCN board
2 ===========================
4 Created 05/24/2006 Haiying Wang
5 -------------------------------
9 The 86xx HPCN code base is known to compile using:
10 Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
12 $ make MPC8641HPCN_config
13 Configuring for MPC8641HPCN board...
18 2. Switch and Jumper Setting
19 ----------------------------
21 J14 Pins 1-2 (near plcc32 socket)
24 SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
30 SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
33 SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
41 SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
43 SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
44 0100000 :: VCORE = 1.11V
45 SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
48 SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
49 SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
50 SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
52 SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
53 0 :: boot from PromJet
54 SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
55 halves (virtual banks)
57 SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
58 SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
60 SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
61 SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
63 SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
64 SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
65 SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
66 SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
67 SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
68 SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
70 SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
71 SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
72 SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
73 SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
74 SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
75 SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
76 SW8(7) = 1 ACPWR = 1 :: non-battery
77 SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
82 The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
83 It is possible to use either half to boot using u-boot. Switch 5 bit 2
84 is used for this purpose.
86 0xEF800000 to 0xEFBFFFFF - 4MB
87 0xEFC00000 to 0xEFFFFFFF - 4MB
88 When this bit is 0, U-Boot is at 0xEFF00000.
89 When this bit is 1, U-Boot is at 0xEFB00000.
91 Use the above mentioned flash commands to program the other half, and
92 use switch 5, bit 2 to alternate between the halves. Note: The booting
93 version of U-Boot will always be at 0xEFF00000.
95 To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
97 tftp 1000000 u-boot.bin
99 erase eff00000 +$filesize
100 cp.b 1000000 eff00000 $filesize
102 or use tftpflash command:
105 To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
107 tftp 1000000 u-boot.bin
108 erase efb00000 +$filesize
109 cp.b 1000000 efb00000 $filesize
114 NOTE: RIO and PCI are mutually exclusive, so they share an address
116 Memory Range Device Size
117 ------------ ------ ----
118 0x0000_0000 0x7fff_ffff DDR 2G
119 0x8000_0000 0x9fff_ffff RIO MEM 512M
120 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
121 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
122 0xffe0_0000 0xffef_ffff CCSR 1M
123 0xffdf_0000 0xffdf_7fff PIXIS 8K
124 0xffdf_8000 0xffdf_ffff CF 8K
125 0xf840_0000 0xf840_3fff Stack space 32K
126 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
127 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
128 0xef80_0000 0xefff_ffff Flash 8M
130 5. pixis_reset command
132 A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
133 using the FPGA sequencer. When the board restarts, it has the option
134 of using either the current or alternate flash bank as the boot
135 image, with or without the watchdog timer enabled, and finally with
136 or without frequency changes.
142 pixis_reset altbank wd
143 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
144 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
148 /* reset to current bank, like "reset" command */
151 /* reset board but use the to alternate flash bank */
154 /* reset board, use alternate flash bank with watchdog timer enabled*/
155 pixis_reset altbank wd
157 /* reset board to alternate bank with frequency changed.
158 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
160 pixis-reset altbank cf 40 2.5 10
162 Valid clock choices are in the 8641 Reference Manuals.