1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on corenet_ds.c
9 #include <linux/compiler.h>
11 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_law.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/fsl_portals.h>
17 #include <asm/fsl_liodn.h>
22 #include "../common/eeprom.h"
24 #define GPIO_OPENDRAIN 0x30000000
25 #define GPIO_DIR 0x3c000004
26 #define GPIO_INITIAL 0x30000000
27 #define GPIO_VGA_SWITCH 0x00001000
31 printf("Board: CYRUS\n");
36 int board_early_init_f(void)
38 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
39 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
42 * Only use DDR1_MCK0/3 and DDR2_MCK0/3
43 * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
44 * the noise introduced by these unterminated and unused clock pairs.
46 setbits_be32(&gur->ddrclkdr, 0x001B001B);
48 /* Set GPIO reset lines to open-drain, tristate */
49 setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
50 setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
52 /* Set GPIO Direction */
53 setbits_be32(&pgpio->gpdir, GPIO_DIR);
58 int board_early_init_r(void)
60 fsl_lbc_t *lbc = LBC_BASE_ADDR;
62 out_be32(&lbc->lbcr, 0);
63 /* 1 clock LALE cycle */
64 out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR);
68 #ifdef CONFIG_SYS_DPAA_QBMAN
69 setup_qbman_portals();
80 int ft_board_setup(void *blob, bd_t *bd)
85 ft_cpu_setup(blob, bd);
87 base = env_get_bootm_low();
88 size = env_get_bootm_size();
90 fdt_fixup_memory(blob, (u64)base, (u64)size);
93 pci_of_setup(blob, bd);
96 fdt_fixup_liodn(blob);
97 fsl_fdt_fixup_dr_usb(blob, bd);
99 #ifdef CONFIG_SYS_DPAA_FMAN
100 fdt_fixup_fman_ethernet(blob);
106 int mac_read_from_eeprom(void)
108 init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
109 CONFIG_SYS_I2C_EEPROM_ADDR,
110 CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
112 return mac_read_from_eeprom_common();