3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. Rights for redistribution and usage in source and binary
6 # forms are granted according to the OpenSSL license.
7 # ====================================================================
9 # SHA256/512_Transform for Itanium.
11 # sha512_block runs in 1003 cycles on Itanium 2, which is almost 50%
12 # faster than gcc and >60%(!) faster than code generated by HP-UX
13 # compiler (yes, HP-UX is generating slower code, because unlike gcc,
14 # it failed to deploy "shift right pair," 'shrp' instruction, which
15 # substitutes for 64-bit rotate).
17 # 924 cycles long sha256_block outperforms gcc by over factor of 2(!)
18 # and HP-UX compiler - by >40% (yes, gcc won sha512_block, but lost
19 # this one big time). Note that "formally" 924 is about 100 cycles
20 # too much. I mean it's 64 32-bit rounds vs. 80 virtually identical
21 # 64-bit ones and 1003*64/80 gives 802. Extra cycles, 2 per round,
22 # are spent on extra work to provide for 32-bit rotations. 32-bit
23 # rotations are still handled by 'shrp' instruction and for this
24 # reason lower 32 bits are deposited to upper half of 64-bit register
25 # prior 'shrp' issue. And in order to minimize the amount of such
26 # operations, X[16] values are *maintained* with copies of lower
27 # halves in upper halves, which is why you'll spot such instructions
28 # as custom 'mux2', "parallel 32-bit add," 'padd4' and "parallel
29 # 32-bit unsigned right shift," 'pshr4.u' instructions here.
31 # Rules of engagement.
33 # There is only one integer shifter meaning that if I have two rotate,
34 # deposit or extract instructions in adjacent bundles, they shall
35 # split [at run-time if they have to]. But note that variable and
36 # parallel shifts are performed by multi-media ALU and *are* pairable
37 # with rotates [and alike]. On the backside MMALU is rather slow: it
38 # takes 2 extra cycles before the result of integer operation is
39 # available *to* MMALU and 2(*) extra cycles before the result of MM
40 # operation is available "back" *to* integer ALU, not to mention that
41 # MMALU itself has 2 cycles latency. However! I explicitly scheduled
42 # these MM instructions to avoid MM stalls, so that all these extra
43 # latencies get "hidden" in instruction-level parallelism.
45 # (*) 2 cycles on Itanium 1 and 1 cycle on Itanium 2. But I schedule
46 # for 2 in order to provide for best *overall* performance,
47 # because on Itanium 1 stall on MM result is accompanied by
48 # pipeline flush, which takes 6 cycles:-(
50 # Resulting performance numbers for 900MHz Itanium 2 system:
52 # The 'numbers' are in 1000s of bytes per second processed.
53 # type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes
54 # sha1(*) 6210.14k 20376.30k 52447.83k 85870.05k 105478.12k
55 # sha256 7476.45k 20572.05k 41538.34k 56062.29k 62093.18k
56 # sha512 4996.56k 20026.28k 47597.20k 85278.79k 111501.31k
58 # (*) SHA1 numbers are for HP-UX compiler and are presented purely
59 # for reference purposes. I bet it can improved too...
61 # To generate code, pass the file name with either 256 or 512 in its
62 # name and compiler flags.
66 if ($output =~ /512.*\.[s|asm]/) {
74 $func="sha512_block_data_order";
80 } elsif ($output =~ /256.*\.[s|asm]/) {
88 $func="sha256_block_data_order";
94 } else { die "nonsense $output"; }
96 open STDOUT,">$output" || die "can't open $output: $!";
100 for (@ARGV) { $ADDP="add" if (/[\+DD|\-mlp]64/); }
101 } else { $ADDP="add"; }
102 for (@ARGV) { $big_endian=1 if (/\-DB_ENDIAN/);
103 $big_endian=0 if (/\-DL_ENDIAN/); }
104 if (!defined($big_endian))
105 { $big_endian=(unpack('L',pack('N',1))==1); }
108 .ident \"$output, version 1.0\"
109 .ident \"IA-64 ISA artwork by Andy Polyakov <appro\@fy.chalmers.se>\"
117 A=r16; B=r17; C=r18; D=r19;
118 E=r20; F=r21; G=r22; H=r23;
120 s0=r26; s1=r27; t0=r28; t1=r29;
123 input=r48; // 2nd arg
125 sgm0=r50; sgm1=r51; // small constants
127 // void $func (SHA_CTX *ctx, const void *in,size_t num[,int host])
134 { .mmi; alloc pfssave=ar.pfs,3,17,0,16
135 $ADDP ctx=0,r32 // 1st arg
138 { .mmi; $ADDP input=0,r33 // 2nd arg
139 mov num=r34 // 3rd arg
144 { .mib; add r8=0*$SZ,ctx
146 brp.loop.imp .L_first16,.L_first16_ctop
148 { .mib; add r10=2*$SZ,ctx
150 brp.loop.imp .L_rest,.L_rest_ctop
154 { .mmi; $LDW A=[r8],4*$SZ
157 { .mmi; $LDW C=[r10],4*$SZ
159 mov sgm0=$sigma0[2] };;
162 add Ktbl=($TABLE#-.Lpic_point),Ktbl }
165 cmp.ne p15,p14=0,r0 };; // used in sha256_block
168 { .mii; mov sgm1=$sigma1[2]
175 $t0="t0", $t1="t1", $code.=<<___ if ($BITS==32);
176 { .mib; (p14) add r9=1,input
177 (p14) add r10=2,input }
178 { .mib; (p14) add r11=3,input
179 (p15) br.dptk.few .L_host };;
180 { .mmi; (p14) ld1 r8=[input],$SZ
182 { .mmi; (p14) ld1 r10=[r10]
183 (p14) ld1 r11=[r11] };;
184 { .mii; (p14) dep r9=r8,r9,8,8
185 (p14) dep r11=r10,r11,8,8 };;
186 { .mib; (p14) dep X[15]=r9,r11,16,16 };;
188 { .mib; (p15) $LDW X[15]=[input],$SZ // X[i]=*input++
190 { .mib; $LDW K=[Ktbl],$SZ
197 mux2 $t0=A,0x44 };; // copy lower half to upper
198 { .mib; xor T1=T1,r8 // T1=((e & f) ^ (~e & g))
199 _rotr r11=$t1,$Sigma1[0] } // ROTR(e,14)
203 $t0="A", $t1="E", $code.=<<___ if ($BITS==64);
204 { .mmi; $LDW X[15]=[input],$SZ // X[i]=*input++
207 { .mmi; $LDW K=[Ktbl],$SZ
210 { .mmi; xor T1=T1,r8 //T1=((e & f) ^ (~e & g))
212 _rotr r11=$t1,$Sigma1[0] } // ROTR(e,14)
214 mux1 X[15]=X[15],\@rev };; // eliminated in big-endian
217 { .mib; add T1=T1,H // T1=Ch(e,f,g)+h
218 _rotr r8=$t1,$Sigma1[1] } // ROTR(e,18)
219 { .mib; xor T2=T2,r10 // T2=((a & b) ^ (a & c) ^ (b & c))
221 { .mib; xor r11=r8,r11
222 _rotr r9=$t1,$Sigma1[2] } // ROTR(e,41)
225 { .mib; xor r9=r9,r11 // r9=Sigma1(e)
226 _rotr r10=$t0,$Sigma0[0] } // ROTR(a,28)
227 { .mib; add T1=T1,K // T1=Ch(e,f,g)+h+K512[i]
229 { .mib; add T1=T1,r9 // T1+=Sigma1(e)
230 _rotr r11=$t0,$Sigma0[1] } // ROTR(a,34)
233 { .mib; add T1=T1,X[15] // T1+=X[i]
234 _rotr r8=$t0,$Sigma0[2] } // ROTR(a,39)
235 { .mib; xor r10=r10,r11
236 mux2 X[15]=X[15],0x44 };; // eliminated in 64-bit
237 { .mmi; xor r10=r8,r10 // r10=Sigma0(a)
242 add A=A,r10 // T2=Maj(a,b,c)+Sigma0(a)
243 br.ctop.sptk .L_first16 };;
245 { .mib; mov ar.lc=$rounds-17 }
246 { .mib; mov ar.ec=1 };;
250 { .mib; $LDW K=[Ktbl],$SZ
251 _rotr r8=X[15-1],$sigma0[0] } // ROTR(s0,1)
252 { .mib; $ADD X[15]=X[15],X[15-9] // X[i&0xF]+=X[(i+9)&0xF]
253 $SHRU s0=X[15-1],sgm0 };; // s0=X[(i+1)&0xF]>>7
255 _rotr r9=X[15-1],$sigma0[1] } // ROTR(s0,8)
256 { .mib; andcm r10=G,E
257 $SHRU s1=X[15-14],sgm1 };; // s1=X[(i+14)&0xF]>>6
258 { .mmi; xor T1=T1,r10 // T1=((e & f) ^ (~e & g))
260 _rotr r10=X[15-14],$sigma1[0] };;// ROTR(s1,19)
262 _rotr r11=X[15-14],$sigma1[1] }// ROTR(s1,61)
263 { .mib; and r8=A,C };;
265 $t0="t0", $t1="t1", $code.=<<___ if ($BITS==32);
266 // I adhere to mmi; in order to hold Itanium 1 back and avoid 6 cycle
267 // pipeline flush in last bundle. Note that even on Itanium2 the
268 // latter stalls for one clock cycle...
269 { .mmi; xor s0=s0,r9 // s0=sigma0(X[(i+1)&0xF])
271 { .mmi; xor r10=r11,r10
274 xor s1=s1,r10 // s1=sigma1(X[(i+14)&0xF])
275 mux2 $t0=A,0x44 };; // copy lower half to upper
277 _rotr r9=$t1,$Sigma1[0] } // ROTR(e,14)
279 add T1=T1,H // T1=Ch(e,f,g)+h
280 $ADD X[15]=X[15],s0 };; // X[i&0xF]+=sigma0(X[(i+1)&0xF])
282 $t0="A", $t1="E", $code.=<<___ if ($BITS==64);
283 { .mib; xor s0=s0,r9 // s0=sigma0(X[(i+1)&0xF])
284 _rotr r9=$t1,$Sigma1[0] } // ROTR(e,14)
285 { .mib; xor r10=r11,r10
287 { .mib; xor s1=s1,r10 // s1=sigma1(X[(i+14)&0xF])
290 $ADD X[15]=X[15],s0 };; // X[i&0xF]+=sigma0(X[(i+1)&0xF])
293 { .mmi; xor T2=T2,r10 // T2=((a & b) ^ (a & c) ^ (b & c))
295 _rotr r8=$t1,$Sigma1[1] };; // ROTR(e,18)
296 { .mmi; xor r11=r8,r9
297 $ADD X[15]=X[15],s1 // X[i&0xF]+=sigma1(X[(i+14)&0xF])
298 _rotr r9=$t1,$Sigma1[2] } // ROTR(e,41)
301 { .mib; xor r9=r9,r11 // r9=Sigma1(e)
302 _rotr r10=$t0,$Sigma0[0] } // ROTR(a,28)
303 { .mib; add T1=T1,K // T1=Ch(e,f,g)+h+K512[i]
305 { .mib; add T1=T1,r9 // T1+=Sigma1(e)
306 _rotr r11=$t0,$Sigma0[1] } // ROTR(a,34)
309 { .mmi; add T1=T1,X[15] // T1+=X[i]
311 _rotr r8=$t0,$Sigma0[2] };; // ROTR(a,39)
312 { .mmi; xor r10=r8,r10 // r10=Sigma0(a)
317 add A=A,r10 // T2=Maj(a,b,c)+Sigma0(a)
318 br.ctop.sptk .L_rest };;
320 { .mib; add r8=0*$SZ,ctx
322 { .mib; add r10=2*$SZ,ctx
323 add r11=3*$SZ,ctx };;
324 { .mmi; $LDW r32=[r8],4*$SZ
325 $LDW r33=[r9],4*$SZ }
326 { .mmi; $LDW r34=[r10],4*$SZ
328 cmp.ltu p6,p7=1,num };;
329 { .mmi; $LDW r36=[r8],-4*$SZ
331 (p6) add Ktbl=-$SZ*$rounds,Ktbl }
332 { .mmi; $LDW r38=[r10],-4*$SZ
333 $LDW r39=[r11],-4*$SZ
334 (p7) mov ar.lc=lcsave };;
341 { .mmi; $STW [r8]=A,4*$SZ
344 { .mmi; $STW [r10]=C,4*$SZ
349 (p6) add num=-1,num }
352 (p6) br.dptk.many .L_outer };;
354 { .mib; mov pr=prsave,0x1ffff
355 br.ret.sptk.many b0 };;
359 $code =~ s/\`([^\`]*)\`/eval $1/gem;
360 $code =~ s/_rotr(\s+)([^=]+)=([^,]+),([0-9]+)/shrp$1$2=$3,$3,$4/gm;
362 $code =~ s/mux2(\s+)\S+/nop.i$1 0x0/gm;
363 $code =~ s/mux1(\s+)\S+/nop.i$1 0x0/gm if ($big_endian);
368 print<<___ if ($BITS==32);
371 K256: data4 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
372 data4 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
373 data4 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
374 data4 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
375 data4 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
376 data4 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
377 data4 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
378 data4 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
379 data4 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
380 data4 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
381 data4 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
382 data4 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
383 data4 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
384 data4 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
385 data4 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
386 data4 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
387 .size K256#,$SZ*$rounds
389 print<<___ if ($BITS==64);
392 K512: data8 0x428a2f98d728ae22,0x7137449123ef65cd
393 data8 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
394 data8 0x3956c25bf348b538,0x59f111f1b605d019
395 data8 0x923f82a4af194f9b,0xab1c5ed5da6d8118
396 data8 0xd807aa98a3030242,0x12835b0145706fbe
397 data8 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
398 data8 0x72be5d74f27b896f,0x80deb1fe3b1696b1
399 data8 0x9bdc06a725c71235,0xc19bf174cf692694
400 data8 0xe49b69c19ef14ad2,0xefbe4786384f25e3
401 data8 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
402 data8 0x2de92c6f592b0275,0x4a7484aa6ea6e483
403 data8 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
404 data8 0x983e5152ee66dfab,0xa831c66d2db43210
405 data8 0xb00327c898fb213f,0xbf597fc7beef0ee4
406 data8 0xc6e00bf33da88fc2,0xd5a79147930aa725
407 data8 0x06ca6351e003826f,0x142929670a0e6e70
408 data8 0x27b70a8546d22ffc,0x2e1b21385c26c926
409 data8 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
410 data8 0x650a73548baf63de,0x766a0abb3c77b2a8
411 data8 0x81c2c92e47edaee6,0x92722c851482353b
412 data8 0xa2bfe8a14cf10364,0xa81a664bbc423001
413 data8 0xc24b8b70d0f89791,0xc76c51a30654be30
414 data8 0xd192e819d6ef5218,0xd69906245565a910
415 data8 0xf40e35855771202a,0x106aa07032bbd1b8
416 data8 0x19a4c116b8d2d0c8,0x1e376c085141ab53
417 data8 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
418 data8 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
419 data8 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
420 data8 0x748f82ee5defb2fc,0x78a5636f43172f60
421 data8 0x84c87814a1f0ab72,0x8cc702081a6439ec
422 data8 0x90befffa23631e28,0xa4506cebde82bde9
423 data8 0xbef9a3f7b2c67915,0xc67178f2e372532b
424 data8 0xca273eceea26619c,0xd186b8c721c0c207
425 data8 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
426 data8 0x06f067aa72176fba,0x0a637dc5a2c898a6
427 data8 0x113f9804bef90dae,0x1b710b35131c471b
428 data8 0x28db77f523047d84,0x32caab7b40c72493
429 data8 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
430 data8 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
431 data8 0x5fcb6fab3ad6faec,0x6c44198c4a475817
432 .size K512#,$SZ*$rounds