2 # Copyright 2009-2016 The OpenSSL Project Authors. All Rights Reserved.
4 # Licensed under the OpenSSL license (the "License"). You may not use
5 # this file except in compliance with the License. You can obtain a copy
6 # in the file LICENSE in the source distribution or at
7 # https://www.openssl.org/source/license.html
10 # ====================================================================
11 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
12 # project. The module is, however, dual licensed under OpenSSL and
13 # CRYPTOGAMS licenses depending on where you obtain it. For further
14 # details see http://www.openssl.org/~appro/cryptogams/.
15 # ====================================================================
19 # Provided that UltraSPARC VIS instructions are pipe-lined(*) and
20 # pairable(*) with IALU ones, offloading of Xupdate to the UltraSPARC
21 # Graphic Unit would make it possible to achieve higher instruction-
22 # level parallelism, ILP, and thus higher performance. It should be
23 # explicitly noted that ILP is the keyword, and it means that this
24 # code would be unsuitable for cores like UltraSPARC-Tx. The idea is
25 # not really novel, Sun had VIS-powered implementation for a while.
26 # Unlike Sun's implementation this one can process multiple unaligned
27 # input blocks, and as such works as drop-in replacement for OpenSSL
28 # sha1_block_data_order. Performance improvement was measured to be
29 # 40% over pure IALU sha1-sparcv9.pl on UltraSPARC-IIi, but 12% on
30 # UltraSPARC-III. See below for discussion...
32 # The module does not present direct interest for OpenSSL, because
33 # it doesn't provide better performance on contemporary SPARCv9 CPUs,
34 # UltraSPARC-Tx and SPARC64-V[II] to be specific. Those who feel they
35 # absolutely must score on UltraSPARC-I-IV can simply replace
36 # crypto/sha/asm/sha1-sparcv9.pl with this module.
38 # (*) "Pipe-lined" means that even if it takes several cycles to
39 # complete, next instruction using same functional unit [but not
40 # depending on the result of the current instruction] can start
41 # execution without having to wait for the unit. "Pairable"
42 # means that two [or more] independent instructions can be
43 # issued at the very same time.
46 for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
47 if ($bits==64) { $bias=2047; $frame=192; }
48 else { $bias=0; $frame=112; }
51 open STDOUT,">$output";
85 @VK=($VK_00_19,$VK_20_39,$VK_40_59,$VK_60_79);
86 @X=("%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
87 "%f8", "%f9","%f10","%f11","%f12","%f13","%f14","%f15","%f16");
89 # This is reference 2x-parallelized VIS-powered Xupdate procedure. It
90 # covers even K_NN_MM addition...
93 my $K=@VK[($i+16)/20];
96 # [ provided that GSR.alignaddr_offset is 5, $mul contains
97 # 0x100ULL<<32|0x100 value and K_NN_MM are pre-loaded to
98 # chosen registers... ]
100 fxors @X[($j+13)%16],@X[$j],@X[$j] !-1/-1/-1:X[0]^=X[13]
101 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
102 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
103 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
104 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
105 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
106 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
107 ![fxors %f15,%f2,%f2]
108 for %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
109 ![fxors %f0,%f3,%f3] !10/17/12:X[0] dependency
110 fpadd32 $K,@X[$j],%f20
111 std %f20,[$Xfer+`4*$j`]
113 # The numbers delimited with slash are the earliest possible dispatch
114 # cycles for given instruction assuming 1 cycle latency for simple VIS
115 # instructions, such as on UltraSPARC-I&II, 3 cycles latency, such as
116 # on UltraSPARC-III&IV, and 2 cycles latency(*), respectively. Being
117 # 2x-parallelized the procedure is "worth" 5, 8.5 or 6 ticks per SHA1
118 # round. As [long as] FPU/VIS instructions are perfectly pairable with
119 # IALU ones, the round timing is defined by the maximum between VIS
120 # and IALU timings. The latter varies from round to round and averages
121 # out at 6.25 ticks. This means that USI&II should operate at IALU
122 # rate, while USIII&IV - at VIS rate. This explains why performance
123 # improvement varies among processors. Well, given that pure IALU
124 # sha1-sparcv9.pl module exhibits virtually uniform performance of
125 # ~9.3 cycles per SHA1 round. Timings mentioned above are theoretical
126 # lower limits. Real-life performance was measured to be 6.6 cycles
127 # per SHA1 round on USIIi and 8.3 on USIII. The latter is lower than
128 # half-round VIS timing, because there are 16 Xupdate-free rounds,
129 # which "push down" average theoretical timing to 8 cycles...
131 # (*) SPARC64-V[II] was originally believed to have 2 cycles VIS
132 # latency. Well, it might have, but it doesn't have dedicated
133 # VIS-unit. Instead, VIS instructions are executed by other
134 # functional units, ones used here - by IALU. This doesn't
135 # improve effective ILP...
138 # The reference Xupdate procedure is then "strained" over *pairs* of
139 # BODY_NN_MM and kind of modulo-scheduled in respect to X[n]^=X[n+13]
140 # and K_NN_MM addition. It's "running" 15 rounds ahead, which leaves
141 # plenty of room to amortize for read-after-write hazard, as well as
142 # to fetch and align input for the next spin. The VIS instructions are
143 # scheduled for latency of 2 cycles, because there are not enough IALU
144 # instructions to schedule for latency of 3, while scheduling for 1
145 # would give no gain on USI&II anyway.
148 my ($i,$a,$b,$c,$d,$e)=@_;
150 my $k=($j+16+2)%16; # ahead reference
151 my $l=($j+16-2)%16; # behind reference
152 my $K=@VK[($j+16-2)/20];
156 $code.=<<___ if (!($i&1));
159 ld [$Xfer+`4*($i%16)`],$Xi
160 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
163 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
168 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
173 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
175 $code.=<<___ if ($i&1);
178 ld [$Xfer+`4*($i%16)`],$Xi
179 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
182 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
185 fpadd32 $K,@X[$l],%f20 !
188 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
191 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
195 $code.=<<___ if ($i&1 && $i>=2);
196 std %f20,[$Xfer+`4*$l`] !
201 my ($i,$a,$b,$c,$d,$e)=@_;
203 my $k=($j+16+2)%16; # ahead reference
204 my $l=($j+16-2)%16; # behind reference
205 my $K=@VK[($j+16-2)/20];
209 $code.=<<___ if (!($i&1) && $i<64);
211 ld [$Xfer+`4*($i%16)`],$Xi
212 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
215 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
220 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
225 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
227 $code.=<<___ if ($i&1 && $i<64);
229 ld [$Xfer+`4*($i%16)`],$Xi
230 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
233 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
236 fpadd32 $K,@X[$l],%f20 !
239 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
242 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
245 std %f20,[$Xfer+`4*$l`] !
247 $code.=<<___ if ($i==64);
249 ld [$Xfer+`4*($i%16)`],$Xi
250 fpadd32 $K,@X[$l],%f20
257 std %f20,[$Xfer+`4*$l`]
263 $code.=<<___ if ($i>64);
265 ld [$Xfer+`4*($i%16)`],$Xi
280 my ($i,$a,$b,$c,$d,$e)=@_;
282 my $k=($j+16+2)%16; # ahead reference
283 my $l=($j+16-2)%16; # behind reference
284 my $K=@VK[($j+16-2)/20];
288 $code.=<<___ if (!($i&1));
290 ld [$Xfer+`4*($i%16)`],$Xi
291 fxors @X[($j+14)%16],@X[$j+1],@X[$j+1]! 0/ 0/ 0:X[1]^=X[14]
294 fxor @X[($j+2)%16],@X[($j+8)%16],%f18! 1/ 1/ 1:Tmp=X[2,3]^X[8,9]
299 fxor %f18,@X[$j],@X[$j] ! 2/ 4/ 3:X[0,1]^=X[2,3]^X[8,9]
304 faligndata @X[$j],@X[$j],%f18 ! 3/ 7/ 5:Tmp=X[0,1]>>>24
307 fpadd32 @X[$j],@X[$j],@X[$j] ! 4/ 8/ 6:X[0,1]<<=1
309 $code.=<<___ if ($i&1);
311 ld [$Xfer+`4*($i%16)`],$Xi
314 fmul8ulx16 %f18,$fmul,%f18 ! 5/10/ 7:Tmp>>=7, Tmp&=1
317 fpadd32 $K,@X[$l],%f20 !
320 fxors @X[($k+13)%16],@X[$k],@X[$k] !-1/-1/-1:X[0]^=X[13]
323 fxor %f18,@X[$j],@X[$j] ! 8/14/10:X[0,1]|=Tmp
328 std %f20,[$Xfer+`4*$l`] !
332 # If there is more data to process, then we pre-fetch the data for
333 # next iteration in last ten rounds...
335 my ($i,$a,$b,$c,$d,$e)=@_;
341 $code.=<<___ if ($i==70);
343 ld [$Xfer+`4*($i%16)`],$Xi
358 and $nXfer,255,$nXfer
359 alignaddr %g0,$align,%g0
360 add $base,$nXfer,$nXfer
362 $code.=<<___ if ($i==71);
364 ld [$Xfer+`4*($i%16)`],$Xi
376 $code.=<<___ if ($i>=72);
377 faligndata @X[$m],@X[$m+2],@X[$m]
379 ld [$Xfer+`4*($i%16)`],$Xi
384 fpadd32 $VK_00_19,@X[$m],%f20
392 $code.=<<___ if ($i<77);
393 ldd [$inp+`8*($i+1-70)`],@X[2*($i+1-70)]
395 $code.=<<___ if ($i==77); # redundant if $inp was aligned
398 ldd [$inp+$tmp0],@X[16]
400 $code.=<<___ if ($i>=72);
401 std %f20,[$nXfer+`4*$m`]
406 .section ".text",#alloc,#execinstr
410 .long 0x5a827999,0x5a827999 ! K_00_19
411 .long 0x6ed9eba1,0x6ed9eba1 ! K_20_39
412 .long 0x8f1bbcdc,0x8f1bbcdc ! K_40_59
413 .long 0xca62c1d6,0xca62c1d6 ! K_60_79
414 .long 0x00000100,0x00000100
416 .type vis_const,#object
417 .size vis_const,(.-vis_const)
419 .globl sha1_block_data_order
420 sha1_block_data_order:
422 add %fp,$bias-256,$base
425 add %o7,vis_const-1b,$tmp0
427 ldd [$tmp0+0],$VK_00_19
428 ldd [$tmp0+8],$VK_20_39
429 ldd [$tmp0+16],$VK_40_59
430 ldd [$tmp0+24],$VK_60_79
436 sub $base,$bias+$frame,%sp
443 ! X[16] is maintained in FP register bank
444 alignaddr %g0,$align,%g0
452 add $base,$Xfer,$Xfer
456 brz,pt $align,.Laligned
460 faligndata @X[0],@X[2],@X[0]
461 faligndata @X[2],@X[4],@X[2]
462 faligndata @X[4],@X[6],@X[4]
463 faligndata @X[6],@X[8],@X[6]
464 faligndata @X[8],@X[10],@X[8]
465 faligndata @X[10],@X[12],@X[10]
466 faligndata @X[12],@X[14],@X[12]
467 faligndata @X[14],@X[16],@X[14]
472 alignaddr %g0,$tmp0,%g0
473 fpadd32 $VK_00_19,@X[0],%f16
474 fpadd32 $VK_00_19,@X[2],%f18
475 fpadd32 $VK_00_19,@X[4],%f20
476 fpadd32 $VK_00_19,@X[6],%f22
477 fpadd32 $VK_00_19,@X[8],%f24
478 fpadd32 $VK_00_19,@X[10],%f26
479 fpadd32 $VK_00_19,@X[12],%f28
480 fpadd32 $VK_00_19,@X[14],%f30
492 fxors @X[13],@X[0],@X[0]
499 for ($i=0;$i<20;$i++) { &BODY_00_19($i,@V); unshift(@V,pop(@V)); }
500 for (;$i<40;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
501 for (;$i<60;$i++) { &BODY_40_59($i,@V); unshift(@V,pop(@V)); }
502 for (;$i<70;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
505 bz,pn `$bits==32?"%icc":"%xcc"`,.Ltail
508 for (;$i<80;$i++) { &BODY_70_79($i,@V); unshift(@V,pop(@V)); }
516 fxors @X[13],@X[0],@X[0]
522 alignaddr %g0,$tmp0,%g0
530 for($i=70;$i<80;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
546 .type sha1_block_data_order,#function
547 .size sha1_block_data_order,(.-sha1_block_data_order)
548 .asciz "SHA1 block transform for SPARCv9a, CRYPTOGAMS by <appro\@openssl.org>"
552 # Purpose of these subroutines is to explicitly encode VIS instructions,
553 # so that one can compile the module without having to specify VIS
554 # extensions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
555 # Idea is to reserve for option to produce "universal" binary and let
556 # programmer detect if current CPU is VIS capable at run-time.
558 my ($mnemonic,$rs1,$rs2,$rd)=@_;
560 my %visopf = ( "fmul8ulx16" => 0x037,
561 "faligndata" => 0x048,
566 $ref = "$mnemonic\t$rs1,$rs2,$rd";
568 if ($opf=$visopf{$mnemonic}) {
569 foreach ($rs1,$rs2,$rd) {
570 return $ref if (!/%f([0-9]{1,2})/);
573 return $ref if ($1&1);
574 # re-encode for upper double register addressing
579 return sprintf ".word\t0x%08x !%s",
580 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
587 my ($mnemonic,$rs1,$rs2,$rd)=@_;
588 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
589 my $ref="$mnemonic\t$rs1,$rs2,$rd";
591 foreach ($rs1,$rs2,$rd) {
592 if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
593 else { return $ref; }
595 return sprintf ".word\t0x%08x !%s",
596 0x81b00300|$rd<<25|$rs1<<14|$rs2,
600 $code =~ s/\`([^\`]*)\`/eval $1/gem;
601 $code =~ s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),(%f[0-9]{1,2}),(%f[0-9]{1,2})/
604 $code =~ s/\b(alignaddr)\s+(%[goli][0-7]),(%[goli][0-7]),(%[goli][0-7])/
605 &unalignaddr($1,$2,$3,$4)