3 # ====================================================================
4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
9 # Hardware SPARC T4 support by David S. Miller <davem@davemloft.net>.
10 # ====================================================================
12 # Performance improvement is not really impressive on pre-T1 CPU: +8%
13 # over Sun C and +25% over gcc [3.3]. While on T1, a.k.a. Niagara, it
14 # turned to be 40% faster than 64-bit code generated by Sun C 5.8 and
15 # >2x than 64-bit code generated by gcc 3.4. And there is a gimmick.
16 # X[16] vector is packed to 8 64-bit registers and as result nothing
17 # is spilled on stack. In addition input data is loaded in compact
18 # instruction sequence, thus minimizing the window when the code is
19 # subject to [inter-thread] cache-thrashing hazard. The goal is to
20 # ensure scalability on UltraSPARC T1, or rather to avoid decay when
21 # amount of active threads exceeds the number of physical cores.
23 # SPARC T4 SHA1 hardware achieves 3.72 cycles per byte, which is 3.1x
24 # faster than software. Multi-process benchmark saturates at 11x
25 # single-process result on 8-core processor, or ~9GBps per 2.85GHz
29 open STDOUT,">$output";
31 @X=("%o0","%o1","%o2","%o3","%o4","%o5","%g1","%o7");
45 @K=($K_00_19,$K_20_39,$K_40_59,$K_60_79);
55 my ($i,$a,$b,$c,$d,$e)=@_;
56 my $xi=($i&1)?@X[($i/2)%8]:$Xi;
74 " srlx @X[(($i+1)/2)%8],32,$Xi\n";
82 my ($i,$a,$b,$c,$d,$e)=@_;
93 sllx @X[($j+6)%8],32,$Xi ! Xupdate($i)
94 xor @X[($j+1)%8],@X[$j%8],@X[$j%8]
95 srlx @X[($j+7)%8],32,$tmp1
96 xor @X[($j+4)%8],@X[$j%8],@X[$j%8]
99 add @K[$i/20],$e,$e !!
100 xor $Xi,@X[$j%8],@X[$j%8]
102 add @X[$j%8],@X[$j%8],@X[$j%8]
104 andn @X[$j%8],$rot1m,@X[$j%8]
106 or $Xi,@X[$j%8],@X[$j%8]
112 my ($i,$a,$b,$c,$d,$e)=@_;
119 $code.="\tsrlx @X[($i/2)%8],32,$xi\n";
136 my ($i,$a,$b,$c,$d,$e)=@_;
143 $code.="\tsrlx @X[($i/2)%8],32,$xi\n";
159 my ($i,$a,$b,$c,$d,$e)=@_;
166 $code.="\tsrlx @X[($i/2)%8],32,$xi\n";
184 #include "sparc_arch.h"
187 .register %g2,#scratch
188 .register %g3,#scratch
191 .section ".text",#alloc,#execinstr
198 .globl sha1_block_data_order
199 sha1_block_data_order:
200 SPARC_LOAD_ADDRESS_LEAF(OPENSSL_sparcv9cap_P,%g1,%g5)
201 ld [%g1+4],%g1 ! OPENSSL_sparcv9cap_P[1]
203 andcc %g1, CFR_SHA1, %g0
207 ld [%o0 + 0x00], %f0 ! load context
212 bne,pn %icc, .Lhwunaligned
216 ldd [%o1 + 0x00], %f8
217 ldd [%o1 + 0x08], %f10
218 ldd [%o1 + 0x10], %f12
219 ldd [%o1 + 0x18], %f14
220 ldd [%o1 + 0x20], %f16
221 ldd [%o1 + 0x28], %f18
222 ldd [%o1 + 0x30], %f20
223 subcc %o2, 1, %o2 ! done yet?
224 ldd [%o1 + 0x38], %f22
226 prefetch [%o1 + 63], 20
228 .word 0x81b02820 ! SHA1
230 bne,pt SIZE_T_CC, .Lhw_loop
234 st %f0, [%o0 + 0x00] ! store context
243 alignaddr %o1, %g0, %o1
245 ldd [%o1 + 0x00], %f10
247 ldd [%o1 + 0x08], %f12
248 ldd [%o1 + 0x10], %f14
249 ldd [%o1 + 0x18], %f16
250 ldd [%o1 + 0x20], %f18
251 ldd [%o1 + 0x28], %f20
252 ldd [%o1 + 0x30], %f22
253 ldd [%o1 + 0x38], %f24
254 subcc %o2, 1, %o2 ! done yet?
255 ldd [%o1 + 0x40], %f26
257 prefetch [%o1 + 63], 20
259 faligndata %f10, %f12, %f8
260 faligndata %f12, %f14, %f10
261 faligndata %f14, %f16, %f12
262 faligndata %f16, %f18, %f14
263 faligndata %f18, %f20, %f16
264 faligndata %f20, %f22, %f18
265 faligndata %f22, %f24, %f20
266 faligndata %f24, %f26, %f22
268 .word 0x81b02820 ! SHA1
270 bne,pt SIZE_T_CC, .Lhwunaligned_loop
271 for %f26, %f26, %f10 ! %f10=%f26
278 save %sp,-STACK_FRAME,%sp
283 sllx $rot1m,32,$rot1m
293 sethi %hi(0x5a827999),$K_00_19
294 or $K_00_19,%lo(0x5a827999),$K_00_19
295 sethi %hi(0x6ed9eba1),$K_20_39
296 or $K_20_39,%lo(0x6ed9eba1),$K_20_39
297 sethi %hi(0x8f1bbcdc),$K_40_59
298 or $K_40_59,%lo(0x8f1bbcdc),$K_40_59
299 sethi %hi(0xca62c1d6),$K_60_79
300 or $K_60_79,%lo(0xca62c1d6),$K_60_79
311 subcc %g0,$tmp1,$tmp2 ! should be 64-$tmp1, but -$tmp1 works too
316 sllx @X[0],$tmp1,@X[0]
317 ldx [$tmp0+64],$tmp64
321 srlx @X[$i+1],$tmp2,$Xi
322 sllx @X[$i+1],$tmp1,@X[$i+1]
327 srlx $tmp64,$tmp2,$tmp64
328 or $tmp64,@X[7],@X[7]
332 for ($i=0;$i<16;$i++) { &BODY_00_15($i,@V); unshift(@V,pop(@V)); }
333 for (;$i<20;$i++) { &BODY_16_19($i,@V); unshift(@V,pop(@V)); }
334 for (;$i<40;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
335 for (;$i<60;$i++) { &BODY_40_59($i,@V); unshift(@V,pop(@V)); }
336 for (;$i<80;$i++) { &BODY_20_39($i,@V); unshift(@V,pop(@V)); }
363 .type sha1_block_data_order,#function
364 .size sha1_block_data_order,(.-sha1_block_data_order)
365 .asciz "SHA1 block transform for SPARCv9, CRYPTOGAMS by <appro\@openssl.org>"
369 # Purpose of these subroutines is to explicitly encode VIS instructions,
370 # so that one can compile the module without having to specify VIS
371 # extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
372 # Idea is to reserve for option to produce "universal" binary and let
373 # programmer detect if current CPU is VIS capable at run-time.
375 my ($mnemonic,$rs1,$rs2,$rd)=@_;
377 my %visopf = ( "faligndata" => 0x048,
380 $ref = "$mnemonic\t$rs1,$rs2,$rd";
382 if ($opf=$visopf{$mnemonic}) {
383 foreach ($rs1,$rs2,$rd) {
384 return $ref if (!/%f([0-9]{1,2})/);
387 return $ref if ($1&1);
388 # re-encode for upper double register addressing
393 return sprintf ".word\t0x%08x !%s",
394 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
401 my ($mnemonic,$rs1,$rs2,$rd)=@_;
402 my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
403 my $ref="$mnemonic\t$rs1,$rs2,$rd";
405 foreach ($rs1,$rs2,$rd) {
406 if (/%([goli])([0-7])/) { $_=$bias{$1}+$2; }
407 else { return $ref; }
409 return sprintf ".word\t0x%08x !%s",
410 0x81b00300|$rd<<25|$rs1<<14|$rs2,
414 foreach (split("\n",$code)) {
415 s/\`([^\`]*)\`/eval $1/ge;
417 s/\b(f[^\s]*)\s+(%f[0-9]{1,2}),\s*(%f[0-9]{1,2}),\s*(%f[0-9]{1,2})/
420 s/\b(alignaddr)\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
421 &unalignaddr($1,$2,$3,$4)