3 # ====================================================================
4 # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
5 # project. The module is, however, dual licensed under OpenSSL and
6 # CRYPTOGAMS licenses depending on where you obtain it. For further
7 # details see http://www.openssl.org/~appro/cryptogams/.
8 # ====================================================================
10 # sha1_block procedure for ARMv4.
14 # Size/performance trade-off
15 # ====================================================================
16 # impl size in bytes comp cycles[*] measured performance
17 # ====================================================================
19 # armv4-small 392/+29% 1958/+64% 2250/+96%
20 # armv4-compact 740/+89% 1552/+26% 1840/+22%
21 # armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
22 # full unroll ~5100/+260% ~1260/+4% ~1300/+5%
23 # ====================================================================
24 # thumb = same as 'small' but in Thumb instructions[**] and
25 # with recurring code in two private functions;
26 # small = detached Xload/update, loops are folded;
27 # compact = detached Xload/update, 5x unroll;
28 # large = interleaved Xload/update, 5x unroll;
29 # full unroll = interleaved Xload/update, full unroll, estimated[!];
31 # [*] Manually counted instructions in "grand" loop body. Measured
32 # performance is affected by prologue and epilogue overhead,
33 # i-cache availability, branch penalties, etc.
34 # [**] While each Thumb instruction is twice smaller, they are not as
35 # diverse as ARM ones: e.g., there are only two arithmetic
36 # instructions with 3 arguments, no [fixed] rotate, addressing
37 # modes are limited. As result it takes more instructions to do
38 # the same job in Thumb, therefore the code is never twice as
39 # small and always slower.
40 # [***] which is also ~35% better than compiler generated code. Dual-
41 # issue Cortex A8 core was measured to process input block in
46 # Rescheduling for dual-issue pipeline resulted in 13% improvement on
47 # Cortex A8 core and in absolute terms ~870 cycles per input block
48 # [or 13.6 cycles per byte].
52 # Profiler-assisted and platform-specific optimization resulted in 10%
53 # improvement on Cortex A8 core and 12.2 cycles per byte.
57 # Add NEON implementation (see sha1-586.pl for background info). On
58 # Cortex A8 it was measured to process one byte in 6.7 cycles or >80%
59 # faster than integer-only code. Because [fully unrolled] NEON code
60 # is ~2.5x larger and there are some redundant instructions executed
61 # when processing last block, improvement is not as big for smallest
62 # blocks, only ~30%. Snapdragon S4 is a tad faster, 6.4 cycles per
63 # byte, which is also >80% faster than integer-only code. Cortex-A15
64 # is even faster spending 5.6 cycles per byte outperforming integer-
65 # only code by factor of 2.
69 # Add ARMv8 code path performing at 2.35 cpb on Apple A7.
71 while (($output=shift) && ($output!~/^\w[\w\-]*\.\w+$/)) {}
72 open STDOUT,">$output";
91 my ($a,$b,$c,$d,$e,$opt1,$opt2)=@_;
96 add $e,$K,$e,ror#2 @ E+=K_xx_xx
99 eor $t2,$t2,$t3 @ 1 cycle stall
100 eor $t1,$c,$d @ F_xx_xx
102 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
103 eor $t0,$t0,$t2,ror#31
107 add $e,$e,$t0 @ E+=X[i]
112 my ($a,$b,$c,$d,$e)=@_;
118 add $e,$K,$e,ror#2 @ E+=K_00_19
120 orr $t0,$t0,$t1,lsl#8
121 eor $t1,$c,$d @ F_xx_xx
122 orr $t0,$t0,$t2,lsl#16
123 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
124 orr $t0,$t0,$t3,lsl#24
126 ldr $t0,[$inp],#4 @ handles unaligned
127 add $e,$K,$e,ror#2 @ E+=K_00_19
128 eor $t1,$c,$d @ F_xx_xx
129 add $e,$e,$a,ror#27 @ E+=ROR(A,27)
131 rev $t0,$t0 @ byte swap
135 add $e,$e,$t0 @ E+=X[i]
136 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
138 add $e,$e,$t1 @ E+=F_00_19(B,C,D)
143 my ($a,$b,$c,$d,$e)=@_;
144 &Xupdate(@_,"and $t1,$b,$t1,ror#2");
146 eor $t1,$t1,$d,ror#2 @ F_00_19(B,C,D)
147 add $e,$e,$t1 @ E+=F_00_19(B,C,D)
152 my ($a,$b,$c,$d,$e)=@_;
153 &Xupdate(@_,"eor $t1,$b,$t1,ror#2");
155 add $e,$e,$t1 @ E+=F_20_39(B,C,D)
160 my ($a,$b,$c,$d,$e)=@_;
161 &Xupdate(@_,"and $t1,$b,$t1,ror#2","and $t2,$c,$d");
163 add $e,$e,$t1 @ E+=F_40_59(B,C,D)
169 #include "arm_arch.h"
174 .global sha1_block_data_order
175 .type sha1_block_data_order,%function
178 sha1_block_data_order:
179 #if __ARM_MAX_ARCH__>=7
180 sub r3,pc,#8 @ sha1_block_data_order
181 ldr r12,.LOPENSSL_armcap
182 ldr r12,[r3,r12] @ OPENSSL_armcap_P
188 stmdb sp!,{r4-r12,lr}
189 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
190 ldmia $ctx,{$a,$b,$c,$d,$e}
197 mov $e,$e,ror#30 @ [6]
200 for($i=0;$i<5;$i++) {
201 &BODY_00_15(@V); unshift(@V,pop(@V));
205 bne .L_00_15 @ [((11+4)*5+2)*3]
208 &BODY_00_15(@V); unshift(@V,pop(@V));
209 &BODY_16_19(@V); unshift(@V,pop(@V));
210 &BODY_16_19(@V); unshift(@V,pop(@V));
211 &BODY_16_19(@V); unshift(@V,pop(@V));
212 &BODY_16_19(@V); unshift(@V,pop(@V));
215 ldr $K,.LK_20_39 @ [+15+16*4]
216 cmn sp,#0 @ [+3], clear carry to denote 20_39
219 for($i=0;$i<5;$i++) {
220 &BODY_20_39(@V); unshift(@V,pop(@V));
223 teq $Xi,sp @ preserve carry
224 bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
225 bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
228 sub sp,sp,#20*4 @ [+2]
231 for($i=0;$i<5;$i++) {
232 &BODY_40_59(@V); unshift(@V,pop(@V));
236 bne .L_40_59 @ [+((12+5)*5+2)*4]
240 cmp sp,#0 @ set carry to denote 60_79
241 b .L_20_39_or_60_79 @ [+4], spare 300 bytes
243 add sp,sp,#80*4 @ "deallocate" stack frame
244 ldmia $ctx,{$K,$t0,$t1,$t2,$t3}
250 stmia $ctx,{$a,$b,$c,$d,$e}
252 bne .Lloop @ [+18], total 1307
255 ldmia sp!,{r4-r12,pc}
257 ldmia sp!,{r4-r12,lr}
259 moveq pc,lr @ be binary compatible with V4, yet
260 bx lr @ interoperable with Thumb ISA:-)
262 .size sha1_block_data_order,.-sha1_block_data_order
265 .LK_00_19: .word 0x5a827999
266 .LK_20_39: .word 0x6ed9eba1
267 .LK_40_59: .word 0x8f1bbcdc
268 .LK_60_79: .word 0xca62c1d6
269 #if __ARM_MAX_ARCH__>=7
271 .word OPENSSL_armcap_P-sha1_block_data_order
273 .asciz "SHA1 block transform for ARMv4/NEON/ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
276 #####################################################################
280 my @V=($a,$b,$c,$d,$e);
281 my ($K_XX_XX,$Ki,$t0,$t1,$Xfer,$saved_sp)=map("r$_",(8..12,14));
283 my @X=map("q$_",(8..11,0..3));
284 my @Tx=("q12","q13");
285 my ($K,$zero)=("q14","q15");
288 sub AUTOLOAD() # thunk [simplified] x86-style perlasm
289 { my $opcode = $AUTOLOAD; $opcode =~ s/.*:://; $opcode =~ s/_/\./;
291 $arg = "#$arg" if ($arg*1 eq $arg);
292 $code .= "\t$opcode\t".join(',',@_,$arg)."\n";
297 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
299 '&add ($e,$e,$Ki)', # e+=X[i]+K
301 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))',
302 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
303 '&eor ($t1,$t1,$t0)', # F_00_19
304 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
305 '&add ($e,$e,$t1);'. # e+=F_00_19
306 '$j++; unshift(@V,pop(@V));'
311 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
313 '&add ($e,$e,$Ki)', # e+=X[i]+K
314 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15)) if ($j<79)',
315 '&eor ($t1,$t0,$c)', # F_20_39
316 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
317 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
318 '&add ($e,$e,$t1);'. # e+=F_20_39
319 '$j++; unshift(@V,pop(@V));'
324 '($a,$b,$c,$d,$e)=@V;'. # '$code.="@ $j\n";'.
325 '&add ($e,$e,$Ki)', # e+=X[i]+K
327 '&ldr ($Ki,sprintf "[sp,#%d]",4*(($j+1)&15))',
328 '&add ($e,$e,$a,"ror#27")', # e+=ROR(A,27)
332 '&mov ($b,$b,"ror#2")', # b=ROR(b,2)
333 '&add ($e,$e,$t1);'. # e+=F_40_59
334 '$j++; unshift(@V,pop(@V));'
341 my @insns = (&$body,&$body,&$body,&$body);
344 &vext_8 (@X[0],@X[-4&7],@X[-3&7],8); # compose "X[-14]" in "X[0]"
348 &vadd_i32 (@Tx[1],@X[-1&7],$K);
350 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0);
352 &vext_8 (@Tx[0],@X[-1&7],$zero,4); # "X[-3]", 3 words
356 &veor (@X[0],@X[0],@X[-4&7]); # "X[0]"^="X[-16]"
359 &veor (@Tx[0],@Tx[0],@X[-2&7]); # "X[-3]"^"X[-8]"
362 &veor (@Tx[0],@Tx[0],@X[0]); # "X[0]"^="X[-3]"^"X[-8]
365 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer
366 &sub ($Xfer,$Xfer,64) if ($Xi%4==0);
369 &vext_8 (@Tx[1],$zero,@Tx[0],4); # "X[0]"<<96, extract one dword
372 &vadd_i32 (@X[0],@Tx[0],@Tx[0]);
375 &vsri_32 (@X[0],@Tx[0],31); # "X[0]"<<<=1
379 &vshr_u32 (@Tx[0],@Tx[1],30);
382 &vshl_u32 (@Tx[1],@Tx[1],2);
385 &veor (@X[0],@X[0],@Tx[0]);
388 &veor (@X[0],@X[0],@Tx[1]); # "X[0]"^=("X[0]">>96)<<<2
390 foreach (@insns) { eval; } # remaining instructions [if any]
392 $Xi++; push(@X,shift(@X)); # "rotate" X[]
398 my @insns = (&$body,&$body,&$body,&$body);
401 &vext_8 (@Tx[0],@X[-2&7],@X[-1&7],8); # compose "X[-6]"
405 &veor (@X[0],@X[0],@X[-4&7]); # "X[0]"="X[-32]"^"X[-16]"
408 &veor (@X[0],@X[0],@X[-7&7]); # "X[0]"^="X[-28]"
411 &vadd_i32 (@Tx[1],@X[-1&7],$K);
413 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!") if ($Xi%5==0);
415 &veor (@Tx[0],@Tx[0],@X[0]); # "X[-6]"^="X[0]"
418 &vshr_u32 (@X[0],@Tx[0],30);
421 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!"); # X[]+K xfer
422 &sub ($Xfer,$Xfer,64) if ($Xi%4==0);
425 &vsli_32 (@X[0],@Tx[0],2); # "X[0]"="X[-6]"<<<2
427 foreach (@insns) { eval; } # remaining instructions [if any]
429 $Xi++; push(@X,shift(@X)); # "rotate" X[]
435 my @insns = (&$body,&$body,&$body,&$body);
438 &vadd_i32 (@Tx[1],@X[-1&7],$K);
441 &vst1_32 ("{@Tx[1]}","[$Xfer,:128]!");
442 &sub ($Xfer,$Xfer,64);
445 &sub ($K_XX_XX,$K_XX_XX,16); # rewind $K_XX_XX
446 &subeq ($inp,$inp,64); # reload last block to avoid SEGV
447 &vld1_8 ("{@X[-4&7]-@X[-3&7]}","[$inp]!");
450 &vld1_8 ("{@X[-2&7]-@X[-1&7]}","[$inp]!");
453 &vld1_32 ("{$K\[]}","[$K_XX_XX,:32]!"); # load K_00_19
456 &vrev32_8 (@X[-4&7],@X[-4&7]);
458 foreach (@insns) { eval; } # remaining instructions
466 my @insns = (&$body,&$body,&$body,&$body);
469 &vrev32_8 (@X[($Xi-3)&7],@X[($Xi-3)&7]);
472 &vadd_i32 (@X[$Xi&7],@X[($Xi-4)&7],$K);
475 &vst1_32 ("{@X[$Xi&7]}","[$Xfer,:128]!");# X[]+K xfer to IALU
477 foreach (@insns) { eval; }
483 #if __ARM_MAX_ARCH__>=7
487 .type sha1_block_data_order_neon,%function
489 sha1_block_data_order_neon:
491 stmdb sp!,{r4-r12,lr}
492 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
493 @ dmb @ errata #451034 on early Cortex A8
494 @ vstmdb sp!,{d8-d15} @ ABI specification says so
496 sub sp,sp,#64 @ alloca
497 adr $K_XX_XX,.LK_00_19
498 bic sp,sp,#15 @ align for 128-bit stores
500 ldmia $ctx,{$a,$b,$c,$d,$e} @ load context
503 vld1.8 {@X[-4&7]-@X[-3&7]},[$inp]! @ handles unaligned
504 veor $zero,$zero,$zero
505 vld1.8 {@X[-2&7]-@X[-1&7]},[$inp]!
506 vld1.32 {${K}\[]},[$K_XX_XX,:32]! @ load K_00_19
507 vrev32.8 @X[-4&7],@X[-4&7] @ yes, even on
508 vrev32.8 @X[-3&7],@X[-3&7] @ big-endian...
509 vrev32.8 @X[-2&7],@X[-2&7]
510 vadd.i32 @X[0],@X[-4&7],$K
511 vrev32.8 @X[-1&7],@X[-1&7]
512 vadd.i32 @X[1],@X[-3&7],$K
513 vst1.32 {@X[0]},[$Xfer,:128]!
514 vadd.i32 @X[2],@X[-2&7],$K
515 vst1.32 {@X[1]},[$Xfer,:128]!
516 vst1.32 {@X[2]},[$Xfer,:128]!
517 ldr $Ki,[sp] @ big RAW stall
521 &Xupdate_16_31(\&body_00_19);
522 &Xupdate_16_31(\&body_00_19);
523 &Xupdate_16_31(\&body_00_19);
524 &Xupdate_16_31(\&body_00_19);
525 &Xupdate_32_79(\&body_00_19);
526 &Xupdate_32_79(\&body_20_39);
527 &Xupdate_32_79(\&body_20_39);
528 &Xupdate_32_79(\&body_20_39);
529 &Xupdate_32_79(\&body_20_39);
530 &Xupdate_32_79(\&body_20_39);
531 &Xupdate_32_79(\&body_40_59);
532 &Xupdate_32_79(\&body_40_59);
533 &Xupdate_32_79(\&body_40_59);
534 &Xupdate_32_79(\&body_40_59);
535 &Xupdate_32_79(\&body_40_59);
536 &Xupdate_32_79(\&body_20_39);
537 &Xuplast_80(\&body_20_39);
538 &Xloop(\&body_20_39);
539 &Xloop(\&body_20_39);
540 &Xloop(\&body_20_39);
542 ldmia $ctx,{$Ki,$t0,$t1,$Xfer} @ accumulate context
551 stmia $ctx,{$a,$b,$c,$d,$e}
555 @ vldmia sp!,{d8-d15}
556 ldmia sp!,{r4-r12,pc}
557 .size sha1_block_data_order_neon,.-sha1_block_data_order_neon
561 #####################################################################
565 my ($ABCD,$E,$E0,$E1)=map("q$_",(0..3));
566 my @MSG=map("q$_",(4..7));
567 my @Kxx=map("q$_",(8..11));
568 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
571 #if __ARM_MAX_ARCH__>=7
572 .type sha1_block_data_order_armv8,%function
574 sha1_block_data_order_armv8:
576 vstmdb sp!,{d8-d15} @ ABI specification says so
580 vld1.32 {$ABCD},[$ctx]!
581 vld1.32 {$E\[0]},[$ctx]
583 vld1.32 {@Kxx[0]\[]},[r3,:32]!
584 vld1.32 {@Kxx[1]\[]},[r3,:32]!
585 vld1.32 {@Kxx[2]\[]},[r3,:32]!
586 vld1.32 {@Kxx[3]\[]},[r3,:32]
589 vld1.8 {@MSG[0]-@MSG[1]},[$inp]!
590 vld1.8 {@MSG[2]-@MSG[3]},[$inp]!
591 vrev32.8 @MSG[0],@MSG[0]
592 vrev32.8 @MSG[1],@MSG[1]
594 vadd.i32 $W0,@Kxx[0],@MSG[0]
595 vrev32.8 @MSG[2],@MSG[2]
596 vmov $ABCD_SAVE,$ABCD @ offload
599 vadd.i32 $W1,@Kxx[0],@MSG[1]
600 vrev32.8 @MSG[3],@MSG[3]
603 vadd.i32 $W0,@Kxx[$j],@MSG[2]
604 sha1su0 @MSG[0],@MSG[1],@MSG[2]
606 for ($j=0,$i=1;$i<20-3;$i++) {
607 my $f=("c","p","m","p")[$i/5];
611 vadd.i32 $W1,@Kxx[$j],@MSG[3]
612 sha1su1 @MSG[0],@MSG[3]
614 $code.=<<___ if ($i<20-4);
615 sha1su0 @MSG[1],@MSG[2],@MSG[3]
617 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
618 push(@MSG,shift(@MSG)); $j++ if ((($i+3)%5)==0);
623 vadd.i32 $W1,@Kxx[$j],@MSG[3]
632 vadd.i32 $ABCD,$ABCD,$ABCD_SAVE
635 vst1.32 {$ABCD},[$ctx]!
636 vst1.32 {$E\[0]},[$ctx]
640 .size sha1_block_data_order_armv8,.-sha1_block_data_order_armv8
645 #if __ARM_MAX_ARCH__>=7
646 .comm OPENSSL_armcap_P,4,4
651 "sha1c" => 0xf2000c40, "sha1p" => 0xf2100c40,
652 "sha1m" => 0xf2200c40, "sha1su0" => 0xf2300c40,
653 "sha1h" => 0xf3b902c0, "sha1su1" => 0xf3ba0380 );
656 my ($mnemonic,$arg)=@_;
658 if ($arg =~ m/q([0-9]+)(?:,\s*q([0-9]+))?,\s*q([0-9]+)/o) {
659 my $word = $opcode{$mnemonic}|(($1&7)<<13)|(($1&8)<<19)
660 |(($2&7)<<17)|(($2&8)<<4)
661 |(($3&7)<<1) |(($3&8)<<2);
662 # since ARMv7 instructions are always encoded little-endian.
663 # correct solution is to use .inst directive, but older
664 # assemblers don't implement it:-(
665 sprintf ".byte\t0x%02x,0x%02x,0x%02x,0x%02x\t@ %s %s",
666 $word&0xff,($word>>8)&0xff,
667 ($word>>16)&0xff,($word>>24)&0xff,
673 foreach (split($/,$code)) {
674 s/{q([0-9]+)\[\]}/sprintf "{d%d[],d%d[]}",2*$1,2*$1+1/eo or
675 s/{q([0-9]+)\[0\]}/sprintf "{d%d[0]}",2*$1/eo;
677 s/\b(sha1\w+)\s+(q.*)/unsha1($1,$2)/geo;
680 s/\bbx\s+lr\b/.word\t0xe12fff1e/o; # make it possible to compile with -march=armv4
685 close STDOUT; # enforce flush